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Author SHA1 Message Date
Lu Yahan 442192e304 [riscv] Fix Zbb simulator and disassembler error 
Change-Id: I3d88f8c307e0acb87be773ca60233dec35dea67a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5619020
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94358}
 2024-06-11 07:41:37 +00:00
Lu Yahan 526c962953 [riscv] Fix store kHolderV2Index 
Change-Id: I794447b144a3ec67e64247bcc80dde329ec0ea42
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5619033
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94354}
 2024-06-11 07:01:03 +00:00
Lu Yahan 9a3b526ea4 [riscv] Port Turboshaft InstructionSelector part5 
Fix Switch Central Stack error

Change-Id: Id60c33273dfd65219c4e7f3c8fe4eb766264c47d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5574671
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Matthias Liedtke <mliedtke@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94350}
 2024-06-11 01:43:56 +00:00
Lu Yahan 1dfe6017df [riscv][api] Mark v8::PropertyCallbackInfo::Holder() for deprecation 
Port commit ac2230aacf


Change-Id: I47b04397ab0f8366673181abe543260eb427b8f7
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5605477
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94312}
 2024-06-07 11:11:32 +00:00
Lu Yahan 653d93418a [riscv] Add include src/codegen/register.h 
Change-Id: I9f438d71cc5ca6c78c0a509514d1e749a78c7fe0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5601722
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94293}
 2024-06-06 15:35:48 +00:00
Lu Yahan 748ab58023 [riscv] Untag the length field in construct frames 
Port commit 925b3ff47e

Drop unnecessary MacroAssembler::kCountIncludesReceiver
Port commit 492a1d8e2a

Change-Id: I542143ece7fb354167b1e955052aa6779210cc00
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5602115
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94277}
 2024-06-06 08:09:34 +00:00
Lu Yahan b6c9a000f8 [tools] Fix DeprecationWarning: invalid escape sequence 
Change-Id: I88fc7563ed9da508d2f8946627f4ac2e327e0fc9
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5601522
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/main@{#94276}
 2024-06-06 08:08:23 +00:00
Lu Yahan e71e37289c [riscv] Port some changes 
Port commit eb0bb2596a
[builtins] Replace v8::FunctionCallbackInfo::data field with target
Bug: 326505377, 328104148

Port commit 8f7698c838
Use framesize + max outgoing args to check stack limits
Bug: 341216494

Port commit d2d190fb13
[wasm] Support calling imports with the generic export wrapper



Change-Id: Ib8aa34a264c5664fd6b2dd5201196fb8ff323518
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5594238
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94224}
 2024-06-04 08:58:32 +00:00
Lu Yahan 23ad6b1e40 [WASM][JSPI][RISCV] Initial port of JSPI to RISC-V architecture 
Port commit 553a1865dc

Bug: v8:12191

Change-Id: I64072d2c0cad2103adbd6a41d8efcf96149b19cb
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5573112
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94189}
 2024-06-03 07:56:55 +00:00
Lu Yahan d789e57f16 [compiler] Add include "src/codegen/register.h" 
Fix build error

Bug: 343519253

Change-Id: I6f35062762997ddcb6ec72994c5cd29ed84ab1f3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5584379
Commit-Queue: Matthias Liedtke <mliedtke@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Matthias Liedtke <mliedtke@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94170}
 2024-05-31 08:56:26 +00:00
Lu Yahan b7e419def5 [riscv]Fix error about set_if_nan 
Change-Id: Ib6c50773b8923a2bc14f03f600c4228ed3a5c28a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5553033
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94049}
 2024-05-23 09:24:04 +00:00
Lu Yahan 9c63b644d9 [riscv][fastcall] Enable float support on riscv64 simulator 
Add IsReturnFloat64 in EncodedCSignature to support NaN Boxing float32.
In RISC-V float32 need be NaN-Boxed, More details are under riscv spec: https://github.com/riscv/riscv-isa-manual/blob/aaf37804a85f7f1ed147e99e6efb2ffd29916d2a/src/d-st-ext.adoc#nan-boxing-of-narrower-values

Port commit 098f31f495
Port commit a6da816119

Change-Id: I1b4a86e597c29ae9a115aa00fb4f46421a2a55a8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5545261
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Toon Verwaest <verwaest@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#94046}
 2024-05-23 08:38:39 +00:00
Lu Yahan 812d47fa1f [riscv][deoptimizer][wasm] Support Simd128 values 
Port commit 566f734f40

Change-Id: Ief63f9cf9a8f5bd9c66d5db6e75e2086b605fccf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5543443
Reviewed-by: Matthias Liedtke <mliedtke@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93956}
 2024-05-17 03:22:45 +00:00
Lu Yahan 1b4d2ac581 [riscv] Skip turboshaft-test-compare-combine 
incorrect register allocation on riscv

Change-Id: I718f12bc44abb867670f2fadacaa233c0a06be80
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5520278
Reviewed-by: Nico Hartmann <nicohartmann@chromium.org>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93769}
 2024-05-07 12:49:20 +00:00
Lu Yahan 441b356202 [riscv32][turboshaft] Implement some turboshaft instr selector 
Change-Id: I76a66544e849ea7a4acc2629bdec88a451351ba8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5518369
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93768}
 2024-05-07 12:46:32 +00:00
Lu Yahan ab639419ed [riscv][turboshaft] Implement some turboshaft instr selector 
Change-Id: I27f45a5cab418ff66bb2a9b4db7b1f6ffe2b5368
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5517871
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93716}
 2024-05-06 08:10:16 +00:00
Lu Yahan 90982c6653 [arm]Fix incorrect fast api call fp 
Bug: 41492790

Change-Id: I8bd68c8a0c520c794220aa23fcc894a7ebe53863
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5471182
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Victor Gomes <victorgomes@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Cr-Commit-Position: refs/heads/main@{#93512}
 2024-04-23 02:59:38 +00:00
Lu Yahan 509f8073d1 [riscv][fastcall] Allow reentrance to JavaScript 
Bug: 41492790

port commit 5cc77a667d

Change-Id: I78dc6cbda4035cee5c59c04d4e675d11af7385e8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5470544
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93484}
 2024-04-22 07:14:54 +00:00
Lu Yahan 5def3a10ce [riscv][codegen] Introduce MemoryRepresentation::kProtectedPointer 
Port commit a9083da44e

Port commit e7c147b65c
[fastcall] Support throwing exceptions

Bug: v8:14564

Change-Id: I518020cef404236c5d6d237c8bd1d80c659f13a6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5454820
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93479}
 2024-04-20 11:04:21 +00:00
Lu Yahan 5841e18a99 [riscv] Detect zbb/zbs/zba by complier define 
Change-Id: I05103862e187e7116f9b5bdd96a40a15a97296d2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5443166
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93412}
 2024-04-17 11:58:23 +00:00
Lu Yahan f00d378664 [riscv] Using sys_riscv_hwprobe to detect risc-v ISA 
Change-Id: I275c5cd9ffd9c55816c06b92c1d4b46761b5ca1c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5442563
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#93288}
 2024-04-10 11:40:19 +00:00
Lu Yahan 34c564a520 [riscv][wasm] Call on-heap import wrappers via a trampoline 
Port commit f18d6b0452

Bug: v8:14564

Change-Id: I856bc8dbafdda5e2031aec188300b4ee27707126
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5437758
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93279}
 2024-04-10 06:21:41 +00:00
Lu Yahan 6ea594ff71 [riscv] Skip check sv57 when enable pointer compress 
Change-Id: I4332d3849d113af105630c0e20cd2b5e3deb9392
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5430889
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93244}
 2024-04-09 03:56:11 +00:00
Lu Yahan cbc1bd9b97 [riscv][turboshaft] Fix more issues in Turboshaft's builtin pipeline 
Port commit aa116324c5
Bug: v8:12783

Change-Id: I5e15f3feef58f0c188a51c876136eb255075727c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5430887
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93210}
 2024-04-08 01:05:01 +00:00
Lu Yahan ca7e2e7750 [riscv] Add check before using int64_value() 
Fix failed after enable turboshaft-wasm

Change-Id: Idabeb329f26280e7002e743750718076981672fc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5402404
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93099}
 2024-04-01 02:38:38 +00:00
Lu Yahan 2b1bde83e2 [sandbox][riscv64] Fix instruction schedule for sandbox related opcode 
The StoreSandboxedPointer should be kHasSideEffect


Change-Id: I347719433accd61b1434cc67e5fcd2da703a8ba3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5390231
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93054}
 2024-03-27 03:02:16 +00:00
Lu Yahan 18117404da [riscv][turboshaft] Port ISEL unittests part 2 
Port commit e34579cf35
Bug: v8:12783

Change-Id: I69f02eace7a63ef8d8274dd2374ba1cfe7fe30d9
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5390228
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93020}
 2024-03-26 05:50:57 +00:00
Lu Yahan 080b42713c [riscv][interpreter] Microoptimise for-in bytecodes 
Port commit da2d5c2952


Change-Id: I2aa9d7179775db7856653fbc4300bf93d38c02ec
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5381798
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92911}
 2024-03-20 04:16:38 +00:00
Lu Yahan 0734b24393 [riscv][sandbox] Tag entries in the TrustedPointerTable 
Port commit c68f02dc2e
Bug: chromium:40069826

Port commit 897e1a3bbf
[wasm] Move WasmApiFunctionRef to trusted space
Bug: v8:14564

Change-Id: Iaff91921ba78311c5d82e4583258fdbf3d1322d1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5373845
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92836}
 2024-03-15 07:40:11 +00:00
Lu Yahan d76fd9ca2f [riscv] Handle unordered comparison 
Port commit 897e1a3bbf
[wasm] Move WasmApiFunctionRef to trusted space
Bug: v8:14564

Change-Id: Ibdd1c74f631145ab8a3571d4ff5ed4425303ad59
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5364233
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92797}
 2024-03-13 08:52:59 +00:00
Lu Yahan 07024f0c42 [riscv][sandbox] First step towards fine-grained entrypoint tags for builtins 
Port commit 25df12c34d
Bug: chromium:1500887

Port commit 69a0ef2ddd
[sandbox] Use a protected pointer to reference Code from IStream
Bug: chromium:1520333

Change-Id: Ic6d41c77ab9cb2c2a4fb51c4293348d801ef9057
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5360473
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92764}
 2024-03-12 06:29:09 +00:00
Lu Yahan 6959ff7f8d [riscv][heap] Always use MemoryChunk:: for flag names 
And Generalize InstructionSelectorT for Turboshaft on riscv32
Port commit 3c2714d573
Bug: v8:12783

Change-Id: I1683931ba08a9c05944a6c88bbdfda66994a7f9a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5348235
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92677}
 2024-03-06 08:28:28 +00:00
Lu Yahan ec8af07823 Reland "[riscv][sandbox] Generalize indirect pointers" 
This is a reland of commit eb887e8d70

Original change's description:
> [riscv][sandbox] Generalize indirect pointers
>
> Port commit 11c55ef5b4
> Port commit b0ae8877e5
>
> Change-Id: I79cc34a7436c06b3cca44fd02d04cb6989220a67
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5328157
> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
> Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
> Cr-Commit-Position: refs/heads/main@{#92625}

Change-Id: Id2fe5b84409c3cd095cd74e4f94d6b0fac20ebc1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5334543
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92627}
 2024-03-01 07:42:50 +00:00
Yahan Lu 61c730ad5f Revert "[riscv][sandbox] Generalize indirect pointers" 
This reverts commit eb887e8d70.

Reason for revert: Build failed

Original change's description:
> [riscv][sandbox] Generalize indirect pointers
>
> Port commit 11c55ef5b4
> Port commit b0ae8877e5
>
> Change-Id: I79cc34a7436c06b3cca44fd02d04cb6989220a67
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5328157
> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
> Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
> Cr-Commit-Position: refs/heads/main@{#92625}

Change-Id: I5dcdf0637953c610a59765d09794b217fa33f0f3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5333260
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92626}
 2024-03-01 06:30:15 +00:00
Lu Yahan eb887e8d70 [riscv][sandbox] Generalize indirect pointers 
Port commit 11c55ef5b4
Port commit b0ae8877e5

Change-Id: I79cc34a7436c06b3cca44fd02d04cb6989220a67
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5328157
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92625}
 2024-03-01 03:28:28 +00:00
Lu Yahan 37985f43d2 [riscv] fix turboshaft/turboshaft-maglev-frontend 
Change-Id: Ib710f316bbe102136f7c467bba806ec7b190c46e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5323535
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Darius Mercadier <dmercadier@chromium.org>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92540}
 2024-02-27 01:14:59 +00:00
Lu Yahan 90b4b746b9 [riscv][builtins] About fast C calls CLs 
Port commit e19a4024f6
[compiler] Always emit safepoint for fast C calls

Pot commit dab24c4009
Reland "[compiler] Add fake handles slots to safepoint table"

Port commit 1da38a4017
[builtins] Do not use SetIsolateDataSlots::kYes in CEntry

Port commit 13f886c703
[sandbox] Refactor Code::source_position_table

Port commit dd8d0b44d5
[execution] Support stack iteration from fast C calls

Bug: b/40927183
Bug: chromium:325123663
Change-Id: Id50551389440878650be3b5c88cbb48d551f6de1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5319782
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92499}
 2024-02-23 09:37:59 +00:00
Lu Yahan c0a1d2215c [wasm][liftoff][riscv] Fix LoadTaggedPointer 
The previous way to compute the protected_load_pc didn't account for
the possibility of a constant pool getting emitted.

Change-Id: I62da4185a5b5c42cb1e952d8f17d692349e3e15e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5316165
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92468}
 2024-02-22 07:31:59 +00:00
Lu Yahan c08629b2fd [riscv] Enable OOB trap handler 
Port commit 5154f22c8c
Reland "[wasm][mac][arm64] Enable OOB trap handler"

Port commit e312038daf
[wasm] Add trap-handler support for arm64 simulator

Port commit 49d78b893b
Reland "[wasm] Single landing pad for trap handlers"

Change-Id: Id26567a65cde60d2a0e49da1e9cb9f3a71cf1a91
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5227604
Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Mark Seaborn <mseaborn@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92437}
 2024-02-21 02:16:38 +00:00
Lu Yahan 2b7cfa54e6 [riscv] Port some patch 
Port commit 9fb9240759
- Reference Code from InstructionStream via a code pointer

Port commit 8cd1e89fae
- Move runtime-generated Code objects out of the sandbox

Port commit 69a0ef2ddd
- Use a protected pointer to reference Code from IStream

Port commit e8513f4439
- [liftoff] Use WasmDispatchTable for indirect calls


Change-Id: I9330354ceaa30657ed50d2dcae0054e65e1bbd95
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5304570
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92383}
 2024-02-18 08:53:07 +00:00
Lu Yahan 360a56392e [riscv][heap] Check that we do not allocate in fast c calls 
Port commit 391a474d7b

Fast c calls are not allowed to allocate or start a GC. Add DCHECKs
and CHECKs to ensure that this is indeed the case through all of V8.

Wasm-c-api was using fast c calls with allocation as well. We could
either disable the checks for it or simply do not set
fast_c_call_caller_fp for those calls. I chose the latter approach
because then we can ensure the (D)CHECKs hold all the time.

Bug: chromium:1523607


Change-Id: I2fc6e21a8f438e61b121cba6cb03669c89c91920
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5260614
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92161}
 2024-02-02 09:46:07 +00:00
Lu Yahan a70744697a [riscv] Skip turboshaft-maglev-frontend 
RISC-V don't support maglev, so skip turboshaft-maglev-frontend.js

Change-Id: Id4f8be55cd3e90845e0215e66ff2860699640ef4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5252428
Reviewed-by: Victor Gomes <victorgomes@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#92128}
 2024-02-01 03:51:01 +00:00
Lu Yahan e2622f32f4 [maglev] Replace CompareRoot/JumpIf by JumpIfRoot or JumpIfNotRoot 
And remove duplicate functions CompareRootAndJumpIf.

Bug: v8:7700

Change-Id: I9498bf702e634dbfaabf871a0c6a603b165da5d5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5252429
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Victor Gomes <victorgomes@chromium.org>
Cr-Commit-Position: refs/heads/main@{#92096}
 2024-01-31 08:31:10 +00:00
Lu Yahan fec2ec5ad5 [riscv] Prepare splitting of MemoryChunk Metadata and Header 
Port commit 165268cc8d


Change-Id: Idfb42a3d9480ee54fed18242b66660ad8cc0fa58
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5232198
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91966}
 2024-01-24 02:24:08 +00:00
Lu Yahan 674a1b0378 [riscv] Add simd load/store condition in IsLoad/IsStore 
STORE_FP/LOAD_FP can be vl/vs/flw/fld/fsw/fsd.

Change-Id: I7f352254e302c444f23d5050255a320fec8721b3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5210810
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91917}
 2024-01-19 07:43:33 +00:00
Lu Yahan 9d51880cdc [riscv] Use enum for Conditions in base-constants-riscv.h 
Port commit 2f9eac13ac

Bug: v8:7700
Change-Id: I47d0e04afbfdf60a56a0c322dd1733243287b52c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5201079
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91885}
 2024-01-17 12:13:10 +00:00
Lu Yahan 728df91558 [riscv][wasm][liftoff] Optimize in-bounds atomic operations 
Port commit 6fece1bf29

Change-Id: If080c20a6355c1e1f8a5fd7e3f4911c71192e22b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5197210
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91850}
 2024-01-16 06:47:23 +00:00
Lu Yahan 94bfe5ffcb [riscv] Implement InstructionAt 
Change-Id: I37da539e4ee9c57b836a8b0bcd05dd7b11202329
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5190789
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91824}
 2024-01-13 02:30:09 +00:00
Lu Yahan 89318585e2 [riscv][liftoff] Use trapping null 
Port commit 58b43c4a74

Change-Id: I8952e72bcc51433717c22cbc2870a5768400bbb0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5181852
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91748}
 2024-01-10 05:45:00 +00:00
Lu Yahan c82365ef60 [riscv][wasm] Introduce WasmTrustedInstanceData 
Port commit 59acab802a

Port commit 8cf17a14a7
[sandbox] Reference Code from FeedbackVector via code pointer

Port commit 4fa7784b10
[sandbox] Reference Code from OSR feedback vector slots via its wrapper


Change-Id: I88cd9b5f27a856aaf7ad319d55c9bed98eb24e45
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5179912
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91745}
 2024-01-10 00:43:43 +00:00
Lu Yahan a654e27b50 [riscv] Optimize macroassembler with B extension 
Change-Id: I0cfb5ecbe3088815bfdc81c5ade6bf0385483e10
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5147360
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91673}
 2024-01-04 09:27:44 +00:00
Lu Yahan 0f6457db02 [riscv] Fix debug build 
Change-Id: Ic4f89c8fe202484a171c14e7048e22345181761d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5149595
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91639}
 2023-12-25 03:53:46 +00:00
Lu Yahan 84aaa40289 [riscv][builtins] Track topmost script-having execution context 
Port commit 32548386ef

Bug: v8:13825

Change-Id: Ic1c4974f0759c75699532d77031129c77c2ab83a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5147361
Commit-Queue: Igor Sheludko <ishell@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Igor Sheludko <ishell@chromium.org>
Cr-Commit-Position: refs/heads/main@{#91630}
 2023-12-22 10:55:02 +00:00
Lu Yahan b18b6559fc [riscv][turboshaft] Add missing pieces to Turboshaft CSA pipeline 
Port commit 235d5bd74c
port commit ee5adf6f7a

Bug: chromium:1506769
Bug: v8:12783

Change-Id: I1db72e9775e3950b60e3dced3e8ccecfe0e99874
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5129396
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91562}
 2023-12-18 04:31:50 +00:00
Lu Yahan d355a3c41e [riscv] Delete align in kArchStackSlot 
Change-Id: Ib06cfdb38d6e6592a58a4b50be767b2e5062e98c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5087190
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91395}
 2023-12-07 08:21:10 +00:00
Lu Yahan 827f845702 [riscv] Delete kWord32ShiftRightArithmetic in ChangeInt32ToInt64 
Change-Id: Ie5cf3b224013639687b4050f9af276ae85a3f747
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5098430
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91392}
 2023-12-07 07:56:49 +00:00
Lu Yahan 8841ea55de [riscv][builtins] Use CallBuiltin/TailCallBuiltin where possible, pt.2 
Run JS imports on the central stack

Port commit 85fddc8861
Port commit b158ad40dc
Port commit 9b1e5f0eac
Port commit 8de6dcc377


Bug: v8:14496
Bug: v8:12191,v8:13983

Change-Id: Ib617aa0911ee9084e4249371e8fcfbff3cab31b2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5087248
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91390}
 2023-12-07 03:52:18 +00:00
Lu Yahan 86e54fe85f [riscv][builtins][masm] Use CallBuiltin/TailCallBuiltin where possible 
Port commit 063210c08c
Port commit 12203e0c46

Bug: v8:14496

Change-Id: I7cabcbc444b21ff8352cf0aea3dbb55177c398d5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5081171
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91322}
 2023-12-04 12:37:17 +00:00
Lu Yahan 9678b69397 [riscv][builtins] Avoid reloading undefined value in InterpreterEntryTrampoline 
Port commit 40c0f84a38

Bug: v8:9771

Change-Id: Ia7344abc1a00965ad70ea2ca8d85a8e43e0e54bd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5075020
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91269}
 2023-11-30 11:01:49 +00:00
Lu Yahan e4b75314d6 [riscv] Implement ChangeInt32ToInt64 when input is a load 
Change-Id: Ic21d3d26ae1aada790c1ea9c6165750c8ed7a3cc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5066071
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91219}
 2023-11-28 14:46:09 +00:00
Lu Yahan 57c865a143 [riscv][turboshaft] Merge EqualOp into ComparisonOp 
Change-Id: I3b8a8846aafd1ba827c6996158a220fd101274c1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5061589
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91172}
 2023-11-27 06:43:01 +00:00
Lu Yahan bf668e84fb [riscv][jspi][arm64] Port JS central stack switch 
Port commit b158ad40dc
Port commit 9fbc6a0eaa

Bug: v8:13983

Change-Id: I7c03f883c951bd6dd4debb56dd124f461b7266cd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5055995
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91129}
 2023-11-23 08:03:44 +00:00
Lu Yahan eb94c4dc8f [riscv][turboshaft] Port InstructionSelector part4 
Port commit 3c3aca4f42

Bug: v8:12783
Change-Id: I22f2d2b316a5d1e71686a3873ecae80c763f81bf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5051556
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91101}
 2023-11-22 07:26:32 +00:00
Lu Yahan a8c1f72360 [riscv][turboshaft] Port InstructionSelector part 3 
Bug: v8:12783

Change-Id: I2832a60e25fdace05ce52f10ab36fb8688f8576d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5046347
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91100}
 2023-11-22 01:17:29 +00:00
Lu Yahan 21d3e127fc [riscv][wasm] Pass arguments directly to memory.init 
Port commit 200df6f6bf

Bug: v8:14357

Change-Id: I7c593aeae9c60aec2706eee1383693f9cad4444d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5046837
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91071}
 2023-11-21 08:43:02 +00:00
Lu Yahan f95794ade0 [riscv]Reland^5 "[wasm][x64] Run JS imports on the central stack" 
Port commit aef80d12d4

Change-Id: I48e29762125a9cb568e0242b903fc6112d035c15
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5038248
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91012}
 2023-11-17 04:31:14 +00:00
Lu Yahan bf9318f5a5 [riscv] Port InstructionSelector part 3 
Port commit d88fb0fc34

Bug: v8:12783
Change-Id: Ia6b6b5cd67712e677c71709edd3d3c41d9f4449e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5037923
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#91011}
 2023-11-17 04:30:11 +00:00
Lu Yahan 0ed82ef0d3 [riscv][compiler] Generalize InstructionSelectorT for Turboshaft (part 19) 
Port commit c89fb79845

Bug: v8:12783
Change-Id: Ia42eb8db8df57a899afa980958987c3430b291fb
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5032534
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90984}
 2023-11-16 02:43:53 +00:00
Lu Yahan 2fae7bdf1c [riscv] Port InstructionSelector part 2 
Port commit 8b70c9388f

Bug: v8:12783

Change-Id: Ie5ea7d3881a87720f850af3c01a8dd3f673e89b8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5024353
Reviewed-by: Matthias Liedtke <mliedtke@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90983}
 2023-11-16 02:03:39 +00:00
Yahan Lu f38b9f169a Revert "[riscv]Reland^3 '[wasm][x64] Run JS imports on the central stack'" 
This reverts commit c5fdbca6df.

Reason for revert: 083b24225f Revert

Original change's description:
> [riscv]Reland^3 '[wasm][x64] Run JS imports on the central stack'
>
> Port commit be830f359c
>
> Bug: v8:13983
>
> Change-Id: Idde2157e0c506996654b26a16e96dc53cfb60bed
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5028221
> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
> Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
> Cr-Commit-Position: refs/heads/main@{#90907}

Bug: v8:13983
Change-Id: Ic366bbfffd3a460cdcba8c4240bf00a60fc4d508
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5035519
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Cr-Commit-Position: refs/heads/main@{#90982}
 2023-11-16 01:40:13 +00:00
Lu Yahan 57b433b0ed [riscv] Skip cctest test-serialize/StaticRootsPredictableSnapshot 
Change-Id: I17aaf6846fbe60b0b4ae6a38a5cf1637131883c6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5012258
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90955}
 2023-11-15 11:44:52 +00:00
Lu Yahan c5fdbca6df [riscv]Reland^3 '[wasm][x64] Run JS imports on the central stack' 
Port commit be830f359c

Bug: v8:13983

Change-Id: Idde2157e0c506996654b26a16e96dc53cfb60bed
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5028221
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90907}
 2023-11-14 06:36:37 +00:00
Lu Yahan 06e522fbed [riscv] Add Zbb/Zba/Zbs extension 
Change-Id: I5bdabf523947b8c5db7f2a9cf945ce0951fd4123
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5009246
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90882}
 2023-11-13 13:15:49 +00:00
Lu Yahan 6cea197267 [riscv] Enable some SIMD test cases and enable turboshaft/instruction-selection on riscv64 
Change-Id: If9660dd9e9ce7a42d5f59df242da12586a427367
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5013640
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90854}
 2023-11-10 11:48:01 +00:00
Lu Yahan 17e1db6735 [riscv][turboshaft] Port InstructionSelector 
Bug: v8:12783

Change-Id: I13b120d7599920a294040c2a12e26f79ecd976c4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5011169
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90807}
 2023-11-08 10:56:31 +00:00
Lu Yahan 150690d5f6 [riscv][interpreter] Skip spread machinery in default derived constructor 
Port commit 6ee16b764a
Bug: v8:13249

Change-Id: I92d70b1edda21c74429c85269af496954c6e6922
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5009304
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90780}
 2023-11-07 08:31:12 +00:00
Lu Yahan 06d8a985d8 [wasm][riscv] Add platform-specific support for the wasm-to-js wrapper 
Port commit 93bb287c2f

Also add check_nanbox argument to control WriteMem<Float32> in simulator. FSW/C_FSWSP should not be checked and converted.

Bug: v8:14035
Change-Id: I82a675b891abfbbe8cc3d37161617f98321ff321
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4974898
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90657}
 2023-10-30 09:21:13 +00:00
Lu Yahan 8071720747 [riscv][wasm] Also load the real stack limit from the root register 
Port commit d5244423b7

Bug: v8:14393
Change-Id: Ia7c7282ef4ddd7f0722bd0b3bf307ed7c98d3a93
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4983265
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90625}
 2023-10-27 06:01:33 +00:00
Lu Yahan cb922c943b [riscv] skip console-profile-wasm on unsupported platforms 
Change-Id: Ifd0ab81e011a78b7722f29dbb60aa94d425a51b3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4974897
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90600}
 2023-10-26 07:26:03 +00:00
Lu Yahan 65bccd2054 [riscv][regexp] Fix stack check in native code when interrupt was requested 
Port commit 7f1aaf2a1c

Bug: chromium:1488199

Change-Id: I6b2567267cee0b30230b2e42b8606188011b4463
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4975715
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90597}
 2023-10-26 03:49:04 +00:00
Lu Yahan 1f026e2919 [riscv][wasm][liftoff] Use root register for stack checks 
Change-Id: Ic87bf01fdda02da8128aaa2377aa087ccb63b380
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4961064
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90527}
 2023-10-23 08:32:36 +00:00
Lu Yahan 5f5766047c [riscv] Sign extend in JumpIfEqual 
Change-Id: I42a6677cf25c1913b5928b7db5f6991e60845b19
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4945656
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90461}
 2023-10-18 02:48:35 +00:00
Lu Yahan 568a80dac9 [riscv] Reland^2 "[liftoff] Add support for direct C calls" 
Port commit 846b5bfe32

Change-Id: I871859d7af906b7d34b98ddf19ea1b69e0afdf4c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4923322
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90399}
 2023-10-13 00:59:56 +00:00
Lu Yahan efba717140 [riscv] Fix the problem of writing out of bounds memory 
Change-Id: I2feeedbd86d1af2179a13511d36a5d09aa424ea6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4921511
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90317}
 2023-10-10 01:26:04 +00:00
Lu Yahan 715964d7b4 [riscv][compres-ptr] Fix LoadFeedback segment fault 
Change-Id: Id07305855ea1bda68113903003a15aa4ca537733
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4921691
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90316}
 2023-10-10 01:25:00 +00:00
Lu Yahan 78060a278a [riscv][baseline] Cache feedback cell in the unused slot 
Port commit 0d7002280b

Change-Id: I126b113adf8953928a1d90c7d9f25ce3f4865a4d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4903771
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90212}
 2023-09-29 21:26:01 +00:00
Lu Yahan e227fa7978 [maglev] Replace ComareFloat/CompareTagged/CompareObjectType with ****AndJumpIf 
Some arches (like MIPS, and RISC-V) don't have a condition bit, so should avoid using condition flag in common code.

Bug: v8:7700

Change-Id: I11f80638f89a5c1f8c4867b43808fd0121e2871d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4891648
Reviewed-by: Leszek Swirski <leszeks@chromium.org>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Leszek Swirski <leszeks@chromium.org>
Cr-Commit-Position: refs/heads/main@{#90206}
 2023-09-29 08:31:53 +00:00
Lu Yahan a8729a8f5d [riscv] Fix wasm/regress-1484978/ rvv aligned failed 
Change-Id: I2ab3f703f7990f3b97fe87e7abb94b4955b08116
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4898230
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90162}
 2023-09-28 05:58:28 +00:00
Lu Yahan b833ec2335 [riscv][interpreter] Cache FBV in the stack frame 
Port commit 92a8363773

Bug: v8:14328

Change-Id: I8aea2dcb6f0e419447e2b04d1b75c98bc62b3882
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4895850
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90159}
 2023-09-28 02:17:07 +00:00
Lu Yahan b7268ebf39 [maglev] Replace CompareInt32 by CompareInt32AndJumpIf 
Some arches (like MIPS, and RISC-V) don't have a condition bit, so should avoid using condition flag in common code.

Bug: v8:7700

Change-Id: Ie18f8641f4d92a8dc78481641a55a4285c75586d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4876814
Reviewed-by: Leszek Swirski <leszeks@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90119}
 2023-09-25 02:09:13 +00:00
Lu Yahan 956e537a37 [riscv][compiler] Generalize InstructionSelectorT for Turboshaft (part 
17)

Port commit dac5987165

Bug: v8:12783
Change-Id: I40a42b3d2b57674dc3819331e7a2a731233b9047
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4868010
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#90003}
 2023-09-15 04:58:02 +00:00
Lu Yahan b871993c1d [compiler] Generalize InstructionSelectorT for Turboshaft (part 16) 
Port commit d91e7905a3

Bug: v8:12783


Change-Id: I5437490452678876cb644e77f0996f440afde9ed
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4857645
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89914}
 2023-09-12 04:17:29 +00:00
Lu Yahan 6c6baa40dc [riscv][cfi] Split RelocIterator into ro / rw versions 
Port commit 3f963778ad

Bug: v8:13355

Change-Id: Id0fe6a54b6462e182653d4c9dd132262757fb1e0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4852327
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89885}
 2023-09-11 07:56:12 +00:00
Lu Yahan 9ae12e6b21 Reland "[riscv][liftoff][cleanup] Tighten static register type" 
This is a reland of commit f1a74c3bc4

Original change's description:
> [riscv][liftoff][cleanup] Tighten static register type
>
> Port commit 825afa519d
>
> Change-Id: Iff363f95e49207cef480e8f3519ad28de1927c9e
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4841733
> Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
> Cr-Commit-Position: refs/heads/main@{#89806}

Change-Id: I3ab2ed91a47213e77d5d6a14b9167b4686ec0c38
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4845953
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89835}
 2023-09-07 02:33:23 +00:00
Yahan Lu 1e3ed70152 Revert "[riscv][liftoff][cleanup] Tighten static register type" 
This reverts commit f1a74c3bc4.

Reason for revert: Debug check failed

Original change's description:
> [riscv][liftoff][cleanup] Tighten static register type
>
> Port commit 825afa519d
>
> Change-Id: Iff363f95e49207cef480e8f3519ad28de1927c9e
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4841733
> Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
> Cr-Commit-Position: refs/heads/main@{#89806}

Change-Id: I51e644b01bf12c4468929cd4cecc5b9ee7450ce7
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4846350
Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Cr-Commit-Position: refs/heads/main@{#89834}
 2023-09-07 01:16:13 +00:00
Lu Yahan f1a74c3bc4 [riscv][liftoff][cleanup] Tighten static register type 
Port commit 825afa519d

Change-Id: Iff363f95e49207cef480e8f3519ad28de1927c9e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4841733
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89806}
 2023-09-06 04:03:06 +00:00
Lu Yahan 13192d6e10 [riscv][tagged-ptr] Convert more Objects to Tagged<> 
Port commit 064b9a7903

Bug: v8:12710

Change-Id: If076ca5cd9e9d175c20fc3611e03d39c0260404d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4837830
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89780}
 2023-09-05 03:12:00 +00:00
Lu Yahan edb8673dd5 [riscv][simulator] Fix vsll implement 
Refer to riscv-v-spec-11.0 11.6, only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.

Change-Id: Id354a63fb48d9c9740cc7a06e555dadec8e0e151
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4822047
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89689}
 2023-08-29 23:53:32 +00:00
Lu Yahan bdcb632a94 [riscv][compiler] Generalize InstructionSelectorT for Turboshaft (part 13) 
This CL ports more of the instruction selector implementation to
support Turboshaft.

Bug: v8:12783

Change-Id: I252e9883bc86bc8ab6ee10ebeced1a7c233486b6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4819612
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89662}
 2023-08-29 03:40:44 +00:00
Lu Yahan 981f0d656d [riscv] Reduce the vector arch code (Part 8) 
Delete unused arch code.

Change-Id: I45b5dfed1e45c0134a9e48f7618a8fcd929e2da9
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4816308
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#89648}
 2023-08-28 11:43:35 +00:00