From e715b69ab2d4fc2c6db41ddb9b0e271a2b1acfa8 Mon Sep 17 00:00:00 2001 From: Gianguido Sora Date: Fri, 23 Feb 2018 00:02:29 +0100 Subject: [PATCH] added pre3 support --- platform/pre3/acpuclock.c | 367 ++++++++++++++++++++++ platform/pre3/display.c | 73 +++++ platform/pre3/gpio.c | 241 ++++++++++++++ platform/pre3/gpio_hw.h | 181 +++++++++++ platform/pre3/include/platform/iomap.h | 109 +++++++ platform/pre3/include/platform/irqs.h | 170 ++++++++++ platform/pre3/include/platform/machtype.h | 41 +++ platform/pre3/interrupts.c | 159 ++++++++++ platform/pre3/panel.c | 196 ++++++++++++ platform/pre3/panel.h | 46 +++ platform/pre3/platform.c | 126 ++++++++ platform/pre3/rules.mk | 28 ++ project/pre3.mk | 28 ++ target/pre3/atags.c | 82 +++++ target/pre3/gpiokeys.c | 80 +++++ target/pre3/include/target/display.h | 47 +++ target/pre3/include/target/gpiokeys.h | 47 +++ target/pre3/include/target/restart.h | 46 +++ target/pre3/init.c | 67 ++++ target/pre3/rules.mk | 39 +++ target/pre3/tools/makefile | 45 +++ target/pre3/tools/mkheader.c | 316 +++++++++++++++++++ 22 files changed, 2534 insertions(+) create mode 100644 platform/pre3/acpuclock.c create mode 100644 platform/pre3/display.c create mode 100644 platform/pre3/gpio.c create mode 100644 platform/pre3/gpio_hw.h create mode 100644 platform/pre3/include/platform/iomap.h create mode 100644 platform/pre3/include/platform/irqs.h create mode 100644 platform/pre3/include/platform/machtype.h create mode 100644 platform/pre3/interrupts.c create mode 100644 platform/pre3/panel.c create mode 100644 platform/pre3/panel.h create mode 100644 platform/pre3/platform.c create mode 100644 platform/pre3/rules.mk create mode 100644 project/pre3.mk create mode 100644 target/pre3/atags.c create mode 100644 target/pre3/gpiokeys.c create mode 100644 target/pre3/include/target/display.h create mode 100644 target/pre3/include/target/gpiokeys.h create mode 100644 target/pre3/include/target/restart.h create mode 100644 target/pre3/init.c create mode 100644 target/pre3/rules.mk create mode 100755 target/pre3/tools/makefile create mode 100755 target/pre3/tools/mkheader.c diff --git a/platform/pre3/acpuclock.c b/platform/pre3/acpuclock.c new file mode 100644 index 0000000..af16c88 --- /dev/null +++ b/platform/pre3/acpuclock.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define ACPU_806MHZ 42 +#define ACPU_1024MHZ 53 +#define ACPU_1200MHZ 125 +#define ACPU_1400MHZ 73 + +/* Macros to select PLL2 with divide by 1 */ +#define ACPU_SRC_SEL 3 +#define ACPU_SRC_DIV 0 + +#define BIT(n) (1 << (n)) +#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */ +#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5)) +#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */ +#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */ +#define MV(mv) ((mv) / (!((mv) % V_STEP))) +/* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */ +#define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA) + + +/* enum for SDC CLK IDs */ +enum +{ + SDC1_CLK = 19, + SDC1_PCLK = 20, + SDC2_CLK = 21, + SDC2_PCLK = 22, + SDC3_CLK = 23, + SDC3_PCLK = 24, + SDC4_CLK = 25, + SDC4_PCLK = 26 +}; + +/* Zero'th entry is dummy */ +static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK}; +static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK}; + +void spm_init(void) +{ + writel(0x05, MSM_SAW_BASE + 0x10); /* MSM_SPM_REG_SAW_CFG */ + writel(0x18, MSM_SAW_BASE + 0x14); /* MSM_SPM_REG_SAW_SPM_CTL */ + writel(0x00006666, MSM_SAW_BASE + 0x18); /* MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY */ + writel(0xFF000666, MSM_SAW_BASE + 0x1C); /* MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY */ + + writel(0x01, MSM_SAW_BASE + 0x24); /* MSM_SPM_REG_SAW_SLP_CLK_EN */ + writel(0x03, MSM_SAW_BASE + 0x28); /* MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN */ + writel(0x00, MSM_SAW_BASE + 0x2C); /* MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN */ + + writel(0x01, MSM_SAW_BASE + 0x30); /* MSM_SPM_REG_SAW_SLP_CLMP_EN */ + writel(0x00, MSM_SAW_BASE + 0x34); /* MSM_SPM_REG_SAW_SLP_RST_EN */ + writel(0x00, MSM_SAW_BASE + 0x38); /* MSM_SPM_REG_SAW_SPM_MPM_CFG */ +} + +/* Configures msmc2 voltage. vlevel is in mV */ +void msmc2_config(unsigned vlevel) +{ + unsigned val; + val = readl(MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */ + val &= ~0xFF; + val |= VDD_RAW(vlevel); + writel(val, MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */ + + /* Wait for PMIC state to return to idle and for VDD to stabilize */ + while(((readl(MSM_SAW_BASE + 0x0C) >> 0x20) & 0x3) != 0); + udelay(160); +} + +void enable_pll(unsigned num) +{ + unsigned reg_val; + reg_val = readl(PLL_ENA_REG); + reg_val |= (1 << num); + writel(reg_val, PLL_ENA_REG); + /* Wait until PLL is enabled */ + while ((readl(PLL2_STATUS_BASE_REG) & (1 << 16)) == 0); +} + +void acpu_clock_init(void) +{ + unsigned clk, reg_clksel, reg_clkctl, src_sel; + /* Fixing msmc2 voltage */ + spm_init(); + + clk = readl(PLL2_L_VAL_ADDR) & 0xFF; + if (clk == ACPU_806MHZ) + msmc2_config(1100); + else if (clk == ACPU_1024MHZ || clk == ACPU_1200MHZ) + msmc2_config(1200); + else if (clk == ACPU_1400MHZ) + msmc2_config(1250); + + /* Enable pll 2 */ + enable_pll(2); + + reg_clksel = readl(SCSS_CLK_SEL); + + /* CLK_SEL_SRC1NO */ + src_sel = reg_clksel & 1; + + /* Program clock source and divider. */ + reg_clkctl = readl(SCSS_CLK_CTL); + reg_clkctl &= ~(0xFF << (8 * src_sel)); + reg_clkctl |= ACPU_SRC_SEL<< (4 + 8 * src_sel); + reg_clkctl |= ACPU_SRC_DIV<< (0 + 8 * src_sel); + writel(reg_clkctl, SCSS_CLK_CTL); + + /* Toggle clock source. */ + reg_clksel ^= 1; + + /* Program clock source selection. */ + writel(reg_clksel, SCSS_CLK_SEL); +} + +void hsusb_clock_init(void) +{ + int val = 0; + unsigned sh2_own_row2; + unsigned sh2_own_row2_hsusb_mask = (1 << 11); + + sh2_own_row2 = readl(SH2_OWN_ROW2_BASE_REG); + if(sh2_own_row2 & sh2_own_row2_hsusb_mask) + { + /* USB local clock control enabled */ + /* Set value in MD register */ + val = 0x5DF; + writel(val, SH2_USBH_MD_REG); + + /* Set value in NS register */ + val = 1 << 8; + val = val | readl(SH2_USBH_NS_REG); + writel(val, SH2_USBH_NS_REG); + + val = 1 << 11; + val = val | readl(SH2_USBH_NS_REG); + writel(val, SH2_USBH_NS_REG); + + val = 1 << 9; + val = val | readl(SH2_USBH_NS_REG); + writel(val, SH2_USBH_NS_REG); + + val = 1 << 13; + val = val | readl(SH2_USBH_NS_REG); + writel(val, SH2_USBH_NS_REG); + + /* Enable USBH_P_CLK */ + val = 1 << 25; + val = val | readl(SH2_GLBL_CLK_ENA_SC); + writel(val, SH2_GLBL_CLK_ENA_SC); + } + else + { + /* USB local clock control not enabled; use proc comm */ + usb_clock_init(); + } +} + +void adm_enable_clock(void) +{ + unsigned int val=0; + + /* Enable ADM_CLK */ + val = 1 << 5; + val = val | readl(SH2_GLBL_CLK_ENA_SC); + writel(val, SH2_GLBL_CLK_ENA_SC); +} + +void mdp_lcdc_clock_init(void) +{ + unsigned int val = 0; + unsigned sh2_own_apps2; + unsigned sh2_own_apps2_lcdc_mask = (1 << 3); + + sh2_own_apps2 = readl(SH2_OWN_APPS2_BASE_REG); + if(sh2_own_apps2 & sh2_own_apps2_lcdc_mask) + { + /* MDP local clock control enabled */ + /* Select clock source and divider */ + val = 0x29; + val = val | readl(SH2_MDP_NS_REG); + writel(val, SH2_MDP_NS_REG); + + /* Enable MDP source clock(root) */ + val = 1 << 11; + val = val | readl(SH2_MDP_NS_REG); + writel(val, SH2_MDP_NS_REG); + + /* Enable graphics clock(branch) */ + val = 1 << 9; + val = val | readl(SH2_MDP_NS_REG); + writel(val, SH2_MDP_NS_REG); + + /* Enable MDP_P_CLK */ + val = 1 << 6; + val = val | readl(SH2_GLBL_CLK_ENA_2_SC); + writel(val, SH2_GLBL_CLK_ENA_2_SC); + + /* Enable AXI_MDP_CLK */ + val = 1 << 29; + val = val | readl(SH2_GLBL_CLK_ENA_2_SC); + writel(val, SH2_GLBL_CLK_ENA_2_SC); + + /* LCDC local clock control enabled */ + /* Set value in MD register */ + val = 0x1FFF9; + writel(val, SH2_MDP_LCDC_MD_REG); + + /* Set MDP_LCDC_N_VAL in NS register */ + val = 0xFFFA << 16; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Set clock source */ + val = 1; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Set divider */ + val = 3 << 3; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Set MN counter mode */ + val = 2 << 5; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Enable MN counter */ + val = 1 << 8; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Enable mdp_lcdc_src(root) clock */ + val = 1 << 11; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Enable mdp_lcdc_pclk(branch) clock */ + val = 1 << 9; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + + /* Enable mdp_lcdc_pad_pclk(branch) clock */ + val = 1 << 12; + val = val | readl(SH2_MDP_LCDC_NS_REG); + writel(val, SH2_MDP_LCDC_NS_REG); + } + else + { + /* MDP local clock control not enabled; use proc comm */ + mdp_clock_init(122880000); + + /* LCDC local clock control not enabled; use proc comm */ + lcdc_clock_init(27648000); + } +} + +void mddi_pmdh_clock_init(void) +{ + unsigned int val = 0; + unsigned sh2_own_row1; + unsigned sh2_own_row1_pmdh_mask = (1 << 19); + + sh2_own_row1 = readl(SH2_OWN_ROW1_BASE_REG); + if(sh2_own_row1 & sh2_own_row1_pmdh_mask) + { + /* Select clock source and divider */ + val = 1; + val |= (1 << 3); + val = val | readl(SH2_PMDH_NS_REG); + writel(val, SH2_PMDH_NS_REG); + + /* Enable PMDH_SRC (root) signal */ + val = 1 << 11; + val = val | readl(SH2_PMDH_NS_REG); + writel(val, SH2_PMDH_NS_REG); + + /* Enable PMDH_P_CLK */ + val = 1 << 4; + val = val | readl(SH2_GLBL_CLK_ENA_2_SC); + writel(val, SH2_GLBL_CLK_ENA_2_SC); + } + else + { + /* MDDI local clock control not enabled; use proc comm */ + mddi_clock_init(0, 480000000); + } +} + +void ce_clock_init(void) +{ + unsigned int val=0; + + /* Enable CE_CLK */ + val = 1 << 6; + val = val | readl(SH2_GLBL_CLK_ENA_SC); + writel(val, SH2_GLBL_CLK_ENA_SC); +} + +/* Configure MMC clock */ +void clock_config_mmc(uint32_t interface, uint32_t freq) +{ + uint32_t reg = 0; + + if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 ) + { + dprintf(CRITICAL, "Failure setting clock rate for MCLK - " + "clk_rate: %d\n!", freq); + ASSERT(0); + } + + /* enable clock */ + if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 ) + { + dprintf(CRITICAL, "Failure enabling MMC Clock!\n"); + ASSERT(0); + } + + reg |= MMC_BOOT_MCI_CLK_ENABLE; + reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; + reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; + writel( reg, MMC_BOOT_MCI_CLK ); +} + +/* Intialize MMC clock */ +void clock_init_mmc(uint32_t interface) +{ + if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 ) + { + dprintf(CRITICAL, "Failure enabling PCLK!\n"); + ASSERT(0); + } +} + diff --git a/platform/pre3/display.c b/platform/pre3/display.c new file mode 100644 index 0000000..c9f9817 --- /dev/null +++ b/platform/pre3/display.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2010 Travis Geiselbrecht + * + * Copyright (c) 2011 James Sullins + * + * Copyright (c) 2012 xndcn + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static int display_w, display_h; +static void *display_fb; + +int fb_flush(void *arg) +{ + while (1) { + thread_sleep(1); + fbcon_flush(); + } +} +void platform_init_display() +{ + display_fb = fbcon_display()->base; + display_w = 480; + display_h = 800; + + thread_resume(thread_create("fb_flush", &fb_flush, NULL, HIGH_PRIORITY, DEFAULT_STACK_SIZE)); +} + +uint lasty = 0; +void flush(uint starty, uint endy) +{ + if (starty != lasty) { + lasty = starty; + fbcon_flush(); + } +} + +void display_get_info(struct display_info *info) +{ + info->framebuffer = display_fb; + info->format = GFX_FORMAT_RGB_565; + info->width = display_w; + info->height = display_h; + info->stride = display_w; + info->flush = NULL;//flush; + info->rotation = 0; +} diff --git a/platform/pre3/gpio.c b/platform/pre3/gpio.c new file mode 100644 index 0000000..1204944 --- /dev/null +++ b/platform/pre3/gpio.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include "gpio_hw.h" + +typedef struct gpioregs gpioregs; + +struct gpioregs +{ + unsigned out; + unsigned in; + unsigned int_status; + unsigned int_clear; + unsigned int_en; + unsigned int_edge; + unsigned int_pos; + unsigned oe; +}; + +static gpioregs GPIO_REGS[] = { + { + .out = GPIO_OUT_0, + .in = GPIO_IN_0, + .int_status = GPIO_INT_STATUS_0, + .int_clear = GPIO_INT_CLEAR_0, + .int_en = GPIO_INT_EN_0, + .int_edge = GPIO_INT_EDGE_0, + .int_pos = GPIO_INT_POS_0, + .oe = GPIO_OE_0, + }, + { + .out = GPIO_OUT_1, + .in = GPIO_IN_1, + .int_status = GPIO_INT_STATUS_1, + .int_clear = GPIO_INT_CLEAR_1, + .int_en = GPIO_INT_EN_1, + .int_edge = GPIO_INT_EDGE_1, + .int_pos = GPIO_INT_POS_1, + .oe = GPIO_OE_1, + }, + { + .out = GPIO_OUT_2, + .in = GPIO_IN_2, + .int_status = GPIO_INT_STATUS_2, + .int_clear = GPIO_INT_CLEAR_2, + .int_en = GPIO_INT_EN_2, + .int_edge = GPIO_INT_EDGE_2, + .int_pos = GPIO_INT_POS_2, + .oe = GPIO_OE_2, + }, + { + .out = GPIO_OUT_3, + .in = GPIO_IN_3, + .int_status = GPIO_INT_STATUS_3, + .int_clear = GPIO_INT_CLEAR_3, + .int_en = GPIO_INT_EN_3, + .int_edge = GPIO_INT_EDGE_3, + .int_pos = GPIO_INT_POS_3, + .oe = GPIO_OE_3, + }, + { + .out = GPIO_OUT_4, + .in = GPIO_IN_4, + .int_status = GPIO_INT_STATUS_4, + .int_clear = GPIO_INT_CLEAR_4, + .int_en = GPIO_INT_EN_4, + .int_edge = GPIO_INT_EDGE_4, + .int_pos = GPIO_INT_POS_4, + .oe = GPIO_OE_4, + }, + { + .out = GPIO_OUT_5, + .in = GPIO_IN_5, + .int_status = GPIO_INT_STATUS_5, + .int_clear = GPIO_INT_CLEAR_5, + .int_en = GPIO_INT_EN_5, + .int_edge = GPIO_INT_EDGE_5, + .int_pos = GPIO_INT_POS_5, + .oe = GPIO_OE_5, + }, + { + .out = GPIO_OUT_6, + .in = GPIO_IN_6, + .int_status = GPIO_INT_STATUS_6, + .int_clear = GPIO_INT_CLEAR_6, + .int_en = GPIO_INT_EN_6, + .int_edge = GPIO_INT_EDGE_6, + .int_pos = GPIO_INT_POS_6, + .oe = GPIO_OE_6, + }, + { + .out = GPIO_OUT_7, + .in = GPIO_IN_7, + .int_status = GPIO_INT_STATUS_7, + .int_clear = GPIO_INT_CLEAR_7, + .int_en = GPIO_INT_EN_7, + .int_edge = GPIO_INT_EDGE_7, + .int_pos = GPIO_INT_POS_7, + .oe = GPIO_OE_7, + }, +}; + +static gpioregs *find_gpio(unsigned n, unsigned *bit) +{ + if(n > 150) { + *bit = 1 << (n - 151); + return GPIO_REGS + 7; + } + if(n > 133) { + *bit = 1 << (n - 134); + return GPIO_REGS + 6; + } + if(n > 106) { + *bit = 1 << (n - 107); + return GPIO_REGS + 5; + } + if(n > 94) { + *bit = 1 << (n - 95); + return GPIO_REGS + 4; + } + if(n > 67) { + *bit = 1 << (n - 68); + return GPIO_REGS + 3; + } + if(n > 43) { + *bit = 1 << (n - 44); + return GPIO_REGS + 2; + } + if(n > 15) { + *bit = 1 << (n - 16); + return GPIO_REGS + 1; + } + *bit = 1 << n; + return GPIO_REGS + 0; +} + +int gpio_config(unsigned n, unsigned flags) +{ + gpioregs *r; + unsigned b; + unsigned v; + + if ((r = find_gpio(n, &b)) == 0) + return -1; + + v = readl(r->oe); + if (flags & GPIO_OUTPUT) { + writel(v | b, r->oe); + } else { + writel(v & (~b), r->oe); + } + return 0; +} + +void gpio_set(unsigned n, unsigned on) +{ + gpioregs *r; + unsigned b; + unsigned v; + + if((r = find_gpio(n, &b)) == 0) return; + + v = readl(r->out); + if(on) { + writel(v | b, r->out); + } else { + writel(v & (~b), r->out); + } +} + +int gpio_get(unsigned n) +{ + gpioregs *r; + unsigned b; + + if((r = find_gpio(n, &b)) == 0) return 0; + + return (readl(r->in) & b) ? 1 : 0; +} + +void platform_config_interleaved_mode_gpios(void) +{ + /* configure EB2_CS1 through GPIO86 */ + writel (GPIO_ALT_FUNC_PAGE_REG, 0x56); + writel (GPIO_ALT_FUNC_CFG_REG, 0x04); + /* configure the EBI2_BUSY1_N through GPIO115 */ + writel (GPIO_ALT_FUNC_PAGE_REG, 0x73); + writel (GPIO_ALT_FUNC_CFG_REG, 0x08); +} + +/* Enables all gpios passed in table*/ +int platform_gpios_enable(const struct msm_gpio *table, int size) +{ + int rc; + int i; + const struct msm_gpio *g; + for (i = 0; i < size; i++) { + g = table + i; + /* Enable gpio */ + rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE); + if (rc) { + goto err; + } + } + return 0; +err: + return rc; +} + diff --git a/platform/pre3/gpio_hw.h b/platform/pre3/gpio_hw.h new file mode 100644 index 0000000..7d7e722 --- /dev/null +++ b/platform/pre3/gpio_hw.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __PLATFORM_MSM7X30_GPIO_HW_H +#define __PLATFORM_MSM7X30_GPIO_HW_H + +#define MSM_GPIO1_BASE 0xAC001000 +#define MSM_GPIO2_BASE 0xAC101000 + +#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) +#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) + +/* output value */ +#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */ +#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */ +#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */ +#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */ +#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */ +#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */ +#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */ +#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */ + +/* same pin map as above, output enable */ +#define GPIO_OE_0 GPIO1_REG(0x10) +#define GPIO_OE_1 GPIO2_REG(0x08) +#define GPIO_OE_2 GPIO1_REG(0x14) +#define GPIO_OE_3 GPIO1_REG(0x18) +#define GPIO_OE_4 GPIO1_REG(0x1C) +#define GPIO_OE_5 GPIO1_REG(0x54) +#define GPIO_OE_6 GPIO1_REG(0xC8) +#define GPIO_OE_7 GPIO1_REG(0x218) + +/* same pin map as above, input read */ +#define GPIO_IN_0 GPIO1_REG(0x34) +#define GPIO_IN_1 GPIO2_REG(0x20) +#define GPIO_IN_2 GPIO1_REG(0x38) +#define GPIO_IN_3 GPIO1_REG(0x3C) +#define GPIO_IN_4 GPIO1_REG(0x40) +#define GPIO_IN_5 GPIO1_REG(0x44) +#define GPIO_IN_6 GPIO1_REG(0xCC) +#define GPIO_IN_7 GPIO1_REG(0x21C) + +/* same pin map as above, 1=edge 0=level interrup */ +#define GPIO_INT_EDGE_0 GPIO1_REG(0x60) +#define GPIO_INT_EDGE_1 GPIO2_REG(0x50) +#define GPIO_INT_EDGE_2 GPIO1_REG(0x64) +#define GPIO_INT_EDGE_3 GPIO1_REG(0x68) +#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C) +#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0) +#define GPIO_INT_EDGE_6 GPIO1_REG(0xD0) +#define GPIO_INT_EDGE_7 GPIO1_REG(0x240) + +/* same pin map as above, 1=positive 0=negative */ +#define GPIO_INT_POS_0 GPIO1_REG(0x70) +#define GPIO_INT_POS_1 GPIO2_REG(0x58) +#define GPIO_INT_POS_2 GPIO1_REG(0x74) +#define GPIO_INT_POS_3 GPIO1_REG(0x78) +#define GPIO_INT_POS_4 GPIO1_REG(0x7C) +#define GPIO_INT_POS_5 GPIO1_REG(0xBC) +#define GPIO_INT_POS_6 GPIO1_REG(0xD4) +#define GPIO_INT_POS_7 GPIO1_REG(0x228) + +/* same pin map as above, interrupt enable */ +#define GPIO_INT_EN_0 GPIO1_REG(0x80) +#define GPIO_INT_EN_1 GPIO2_REG(0x60) +#define GPIO_INT_EN_2 GPIO1_REG(0x84) +#define GPIO_INT_EN_3 GPIO1_REG(0x88) +#define GPIO_INT_EN_4 GPIO1_REG(0x8C) +#define GPIO_INT_EN_5 GPIO1_REG(0xB8) +#define GPIO_INT_EN_6 GPIO1_REG(0xD8) +#define GPIO_INT_EN_7 GPIO1_REG(0x22C) + +/* same pin map as above, write 1 to clear interrupt */ +#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90) +#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68) +#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94) +#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98) +#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C) +#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4) +#define GPIO_INT_CLEAR_6 GPIO1_REG(0xDC) +#define GPIO_INT_CLEAR_7 GPIO1_REG(0x230) + +/* same pin map as above, 1=interrupt pending */ +#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0) +#define GPIO_INT_STATUS_1 GPIO2_REG(0x70) +#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4) +#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8) +#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC) +#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0) +#define GPIO_INT_STATUS_6 GPIO1_REG(0xE0) +#define GPIO_INT_STATUS_7 GPIO1_REG(0x234) + + +#define GPIO_OUT_VAL_REG_BASE 0xABC00000 +#define GPIO_ALT_FUNC_PAGE_REG (GPIO_OUT_VAL_REG_BASE + 0x20) +#define GPIO_ALT_FUNC_CFG_REG (GPIO_OUT_VAL_REG_BASE + 0x24) + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +#define GPIO38_GPIO_CNTRL 0x175 + +/* GPIO TLMM: Status */ +#define GPIO_ENABLE 0 +#define GPIO_DISABLE 1 + +#define GPIO_CFG(gpio, func, dir, pull, drvstr) \ + ((((gpio) & 0x3FF) << 4) | \ + ((func) & 0xf) | \ + (((dir) & 0x1) << 14) | \ + (((pull) & 0x3) << 15) | \ + (((drvstr) & 0xF) << 17)) + +/** + * struct msm_gpio - GPIO pin description + * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() + * @label - textual label + * + * Usually, GPIO's are operated by sets. + * This struct accumulate all GPIO information in single source + * and facilitete group operations provided by msm_gpios_xxx() + */ +struct msm_gpio { + unsigned gpio_cfg; + const char *label; +}; + +/** + * extract GPIO pin from bit-field used for gpio_tlmm_config + */ +#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff) +#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf) +#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1) +#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3) +#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf) + +#endif diff --git a/platform/pre3/include/platform/iomap.h b/platform/pre3/include/platform/iomap.h new file mode 100644 index 0000000..8bafc03 --- /dev/null +++ b/platform/pre3/include/platform/iomap.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _PLATFORM_MSM7X30_IOMAP_H_ +#define _PLATFORM_MSM7X30_IOMAP_H_ + +#define MSM_UART1_BASE 0xACA00000 +#define MSM_UART2_BASE 0xACB00000 +#define MSM_UART3_BASE 0xACC00000 + +#define MSM_VIC_BASE 0xC0080000 +#define MSM_TMR_BASE 0xC0100000 + +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) +#define SPSS_TIMER_STATUS (MSM_TMR_BASE + 0x88) + +#define GPT_REG(off) (MSM_GPT_BASE + (off)) +#define DGT_REG(off) (MSM_DGT_BASE + (off)) + +#define GPT_MATCH_VAL GPT_REG(0x0000) +#define GPT_COUNT_VAL GPT_REG(0x0004) +#define GPT_ENABLE GPT_REG(0x0008) +#define GPT_CLEAR GPT_REG(0x000C) + +#define DGT_MATCH_VAL DGT_REG(0x0000) +#define DGT_COUNT_VAL DGT_REG(0x0004) +#define DGT_ENABLE DGT_REG(0x0008) +#define DGT_CLEAR DGT_REG(0x000C) +#define DGT_CLK_CTL DGT_REG(0x0010) + +#define HW_REVISION_NUMBER 0xABC00270 + +#define MSM_CSR_BASE 0xC0100000 +#define MSM_GCC_BASE 0xC0182000 + +#define MSM_SDC1_BASE 0xA0400000 +#define MSM_SDC2_BASE 0xA0500000 +#define MSM_SDC3_BASE 0xA3000000 +#define MSM_SDC4_BASE 0xA3100000 + +#define MSM_SHARED_BASE 0xff00000//mmu by bootie.//0x00100000 + +#define MSM_CLK_CTL_BASE 0xAB800000 +#define MSM_CLK_CTL_SH2_BASE 0xABA01000 + +#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off)) +#define REG_SH2_BASE(off) (MSM_CLK_CTL_SH2_BASE + (off)) + +#define SCSS_CLK_CTL 0xC0101004 +#define SCSS_CLK_SEL 0xC0101008 + +#define MSM_USB_BASE 0xA3600000 +#define MSM_CRYPTO_BASE 0xA8400000 + +#define SH2_USBH_MD_REG REG_SH2_BASE(0x2BC) +#define SH2_USBH_NS_REG REG_SH2_BASE(0x2C0) + +#define SH2_MDP_NS_REG REG_SH2_BASE(0x14C) +#define SH2_MDP_LCDC_MD_REG REG_SH2_BASE(0x38C) +#define SH2_MDP_LCDC_NS_REG REG_SH2_BASE(0x390) +#define SH2_MDP_VSYNC_REG REG_SH2_BASE(0x460) +#define SH2_PMDH_NS_REG REG_SH2_BASE(0x8C) + +#define SH2_GLBL_CLK_ENA_SC REG_SH2_BASE(0x3BC) +#define SH2_GLBL_CLK_ENA_2_SC REG_SH2_BASE(0x3C0) + +#define SH2_OWN_ROW1_BASE_REG REG_BASE(0x041C) +#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424) +#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414) + +#define MSM_ADM_BASE 0xAC200000 +#define MSM_ADM_SD_OFFSET 0x00100400 + +#define MSM_SAW_BASE 0xC0102000 + +#define PLL_ENA_REG REG_SH2_BASE(0x0264) +#define PLL2_STATUS_BASE_REG REG_BASE(0x0350) +#define PLL2_L_VAL_ADDR REG_BASE(0x033C) +#endif diff --git a/platform/pre3/include/platform/irqs.h b/platform/pre3/include/platform/irqs.h new file mode 100644 index 0000000..ad58b59 --- /dev/null +++ b/platform/pre3/include/platform/irqs.h @@ -0,0 +1,170 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_7X30_H +#define __ASM_ARCH_MSM_IRQS_7X30_H + +/* MSM ACPU Interrupt Numbers */ + +#define INT_DEBUG_TIMER_EXP 0 +#define INT_GPT0_TIMER_EXP 1 +#define INT_GPT1_TIMER_EXP 2 +#define INT_WDT0_ACCSCSSBARK 3 +#define INT_WDT1_ACCSCSSBARK 4 +#define INT_AVS_SVIC 5 +#define INT_AVS_SVIC_SW_DONE 6 +#define INT_SC_DBG_RX_FULL 7 +#define INT_SC_DBG_TX_EMPTY 8 +#define INT_SC_PERF_MON 9 +#define INT_AVS_REQ_DOWN 10 +#define INT_AVS_REQ_UP 11 +#define INT_SC_ACG 12 +/* SCSS_VICFIQSTS1[13:15] are RESERVED */ +#define INT_L2_SVICCPUIRPTREQ 16 +#define INT_L2_SVICDMANSIRPTREQ 17 +#define INT_L2_SVICDMASIRPTREQ 18 +#define INT_L2_SVICSLVIRPTREQ 19 +#define INT_AD5A_MPROC_APPS_0 20 +#define INT_AD5A_MPROC_APPS_1 21 +#define INT_A9_M2A_0 22 +#define INT_A9_M2A_1 23 +#define INT_A9_M2A_2 24 +#define INT_A9_M2A_3 25 +#define INT_A9_M2A_4 26 +#define INT_A9_M2A_5 27 +#define INT_A9_M2A_6 28 +#define INT_A9_M2A_7 29 +#define INT_A9_M2A_8 30 +#define INT_A9_M2A_9 31 + +#define INT_AXI_EBI1_SC (32 + 0) +#define INT_IMEM_ERR (32 + 1) +#define INT_AXI_EBI0_SC (32 + 2) +#define INT_PBUS_SC_IRQC (32 + 3) +#define INT_PERPH_BUS_BPM (32 + 4) +#define INT_CC_TEMP_SENSE (32 + 5) +#define INT_UXMC_EBI0 (32 + 6) +#define INT_UXMC_EBI1 (32 + 7) +#define INT_EBI2_OP_DONE (32 + 8) +#define INT_EBI2_WR_ER_DONE (32 + 9) +#define INT_TCSR_SPSS_CE (32 + 10) +#define INT_EMDH (32 + 11) +#define INT_PMDH (32 + 12) +#define INT_MDC (32 + 13) +#define INT_MIDI_TO_SUPSS (32 + 14) +#define INT_LPA_2 (32 + 15) +#define INT_GPIO_GROUP1_SECURE (32 + 16) +#define INT_GPIO_GROUP2_SECURE (32 + 17) +#define INT_GPIO_GROUP1 (32 + 18) +#define INT_GPIO_GROUP2 (32 + 19) +#define INT_MPRPH_SOFTRESET (32 + 20) +#define INT_PWB_I2C (32 + 21) +#define INT_PWB_I2C_2 (32 + 22) +#define INT_TSSC_SAMPLE (32 + 23) +#define INT_TSSC_PENUP (32 + 24) +#define INT_TCHSCRN_SSBI (32 + 25) +#define INT_FM_RDS (32 + 26) +#define INT_KEYSENSE (32 + 27) +#define INT_USB_OTG_HS (32 + 28) +#define INT_USB_OTG_HS2 (32 + 29) +#define INT_USB_OTG_HS3 (32 + 30) +#define INT_RESERVED_BIT31 (32 + 31) + +#define INT_SPI_OUTPUT (64 + 0) +#define INT_SPI_INPUT (64 + 1) +#define INT_SPI_ERROR (64 + 2) +#define INT_UART1 (64 + 3) +#define INT_UART1_RX (64 + 4) +#define INT_UART2 (64 + 5) +#define INT_UART2_RX (64 + 6) +#define INT_UART3 (64 + 7) +#define INT_UART3_RX (64 + 8) +#define INT_UART1DM_IRQ (64 + 9) +#define INT_UART1DM_RX (64 + 10) +#define INT_UART2DM_IRQ (64 + 11) +#define INT_UART2DM_RX (64 + 12) +#define INT_TSIF (64 + 13) +#define INT_ADM_SC1 (64 + 14) +#define INT_ADM_SC2 (64 + 15) +#define INT_MDP (64 + 16) +#define INT_VPE (64 + 17) +#define INT_GRP_2D (64 + 18) +#define INT_GRP_3D (64 + 19) +#define INT_ROTATOR (64 + 20) +#define INT_MFC720 (64 + 21) +#define INT_JPEG (64 + 22) +#define INT_VFE (64 + 23) +#define INT_TV_ENC (64 + 24) +#define INT_PMIC_SSBI (64 + 25) +#define INT_MPM_1 (64 + 26) +#define INT_TCSR_SPSS_SAMPLE (64 + 27) +#define INT_TCSR_SPSS_PENUP (64 + 28) +#define INT_MPM_2 (64 + 29) +#define INT_SDC1_0 (64 + 30) +#define INT_SDC1_1 (64 + 31) + +#define INT_SDC3_0 (96 + 0) +#define INT_SDC3_1 (96 + 1) +#define INT_SDC2_0 (96 + 2) +#define INT_SDC2_1 (96 + 3) +#define INT_SDC4_0 (96 + 4) +#define INT_SDC4_1 (96 + 5) +#define INT_PWB_QUP_IN (96 + 6) +#define INT_PWB_QUP_OUT (96 + 7) +#define INT_PWB_QUP_ERR (96 + 8) +/* SCSS_VICFIQSTS3[6:31] are RESERVED */ + +/* Retrofit universal macro names */ +#define INT_ADM_AARM INT_ADM_SC2 +#define INT_USB_HS INT_USB_OTG_HS +#define INT_USB_OTG INT_USB_OTG_HS +#define INT_TCHSCRN1 INT_TSSC_SAMPLE +#define INT_TCHSCRN2 INT_TSSC_PENUP +#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP +#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0 +#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1 +#define INT_MDDI_EXT INT_EMDH +#define INT_MDDI_PRI INT_PMDH +#define INT_MDDI_CLIENT INT_MDC +#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE +#define INT_NAND_OP_DONE INT_EBI2_OP_DONE + +#define NR_MSM_IRQS 128 +#define NR_GPIO_IRQS 182 +#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS) +#define NR_PMIC8058_GPIO_IRQS 40 +#define NR_PMIC8058_MPP_IRQS 12 +#define NR_PMIC8058_MISC_IRQS 8 +#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\ + NR_PMIC8058_MPP_IRQS +\ + NR_PMIC8058_MISC_IRQS) +#define NR_BOARD_IRQS NR_PMIC8058_IRQS + +#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) + +#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */ diff --git a/platform/pre3/include/platform/machtype.h b/platform/pre3/include/platform/machtype.h new file mode 100644 index 0000000..e80c9d0 --- /dev/null +++ b/platform/pre3/include/platform/machtype.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _PLATFORM_MSM7X30_MACHTYPE_H_ +#define _PLATFORM_MSM7X30_MACHTYPE_H_ + +#define LINUX_MACHTYPE_7x30_SURF 2679 +#define LINUX_MACHTYPE_7x30_FFA 2707 +#define LINUX_MACHTYPE_7x30_FLUID 2741 +#define LINUX_MACHTYPE_8x55_SURF 2768 +#define LINUX_MACHTYPE_8x55_FFA 2769 +#define LINUX_MACHTYPE_8x55_SVLTE_FFA 2863 +#define LINUX_MACHTYPE_8x55_SVLTE_SURF 2864 + +#endif diff --git a/platform/pre3/interrupts.c b/platform/pre3/interrupts.c new file mode 100644 index 0000000..f3624db --- /dev/null +++ b/platform/pre3/interrupts.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define VIC_REG(off) (MSM_VIC_BASE + (off)) + +#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_EN0 VIC_REG(0x0010) +#define VIC_INT_EN1 VIC_REG(0x0014) +#define VIC_INT_ENCLEAR0 VIC_REG(0x0020) +#define VIC_INT_ENCLEAR1 VIC_REG(0x0024) +#define VIC_INT_ENSET0 VIC_REG(0x0030) +#define VIC_INT_ENSET1 VIC_REG(0x0034) +#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ +#define VIC_NO_PEND_VAL VIC_REG(0x0060) +#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */ +#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */ +#define VIC_SECURITY0 VIC_REG(0x0070) +#define VIC_SECURITY1 VIC_REG(0x0074) +#define VIC_IRQ_STATUS0 VIC_REG(0x0080) +#define VIC_IRQ_STATUS1 VIC_REG(0x0084) +#define VIC_FIQ_STATUS0 VIC_REG(0x0090) +#define VIC_FIQ_STATUS1 VIC_REG(0x0094) +#define VIC_RAW_STATUS0 VIC_REG(0x00A0) +#define VIC_RAW_STATUS1 VIC_REG(0x00A4) +#define VIC_INT_CLEAR0 VIC_REG(0x00B0) +#define VIC_INT_CLEAR1 VIC_REG(0x00B4) +#define VIC_SOFTINT0 VIC_REG(0x00C0) +#define VIC_SOFTINT1 VIC_REG(0x00C4) +#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ +#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ +#define VIC_IRQ_VEC_WR VIC_REG(0x00D8) +#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */ +#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */ +#define VIC_FIQ_VEC_WR VIC_REG(0x00E4) +#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8) +#define VIC_IRQ_IN_STACK VIC_REG(0x00EC) +#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0) +#define VIC_FIQ_IN_STACK VIC_REG(0x00F4) +#define VIC_TEST_BUS_SEL VIC_REG(0x00F8) + +#define SIRC_REG(off) (MSM_SIRC_BASE + (off)) + +#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */ +#define SIRC_INT_ENABLE SIRC_REG(0x0004) +#define SIRC_INT_ENCLEAR SIRC_REG(0x0008) +#define SIRC_INT_ENSET SIRC_REG(0x000C) +#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */ +#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */ +#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */ +#define SIRC_IRQ0_STATUS SIRC_REG(0x001C) +#define SIRC_IRQ1_STATUS SIRC_REG(0x0020) +#define SIRC_RAW_STATUS SIRC_REG(0x0024) + +struct ihandler { + int_handler func; + void *arg; +}; + +static struct ihandler handler[NR_IRQS]; + +void platform_init_interrupts(void) +{ + writel(0xffffffff, VIC_INT_CLEAR0); + writel(0xffffffff, VIC_INT_CLEAR1); + writel(0, VIC_INT_SELECT0); + writel(0, VIC_INT_SELECT1); + writel(0xffffffff, VIC_INT_TYPE0); + writel(0xffffffff, VIC_INT_TYPE1); + writel(0, VIC_CONFIG); + writel(1, VIC_INT_MASTEREN); +} + +enum handler_return platform_irq(struct arm_iframe *frame) +{ + unsigned num; + enum handler_return ret; + num = readl(VIC_IRQ_VEC_RD); + num = readl(VIC_IRQ_VEC_PEND_RD); + if (num > NR_IRQS) + return 0; + writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0); + ret = handler[num].func(handler[num].arg); + writel(0, VIC_IRQ_VEC_WR); + return ret; +} + +void platform_fiq(struct arm_iframe *frame) +{ + PANIC_UNIMPLEMENTED; +} + +status_t mask_interrupt(unsigned int vector) +{ + unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0; + unsigned bit = 1 << (vector & 31); + writel(bit, reg); + return 0; +} + +status_t unmask_interrupt(unsigned int vector) +{ + unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0; + unsigned bit = 1 << (vector & 31); + writel(bit, reg); + return 0; +} + +void register_int_handler(unsigned int vector, int_handler func, void *arg) +{ + if (vector >= NR_IRQS) + return; + + enter_critical_section(); + handler[vector].func = func; + handler[vector].arg = arg; + exit_critical_section(); +} + diff --git a/platform/pre3/panel.c b/platform/pre3/panel.c new file mode 100644 index 0000000..4800028 --- /dev/null +++ b/platform/pre3/panel.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2007, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include "gpio_hw.h" +#include "panel.h" +#include +#include + +#if DISPLAY_TYPE_MDDI +#include + +#define MDDI_CLIENT_CORE_BASE 0x108000 +#define LCD_CONTROL_BLOCK_BASE 0x110000 +#define SPI_BLOCK_BASE 0x120000 +#define I2C_BLOCK_BASE 0x130000 +#define PWM_BLOCK_BASE 0x140000 +#define GPIO_BLOCK_BASE 0x150000 +#define SYSTEM_BLOCK1_BASE 0x160000 +#define SYSTEM_BLOCK2_BASE 0x170000 + + +#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) +#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) +#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) +#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) +#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) +#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) +#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) +#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) +#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) +#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) +#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) +#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) +#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) +#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) +#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) +#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) +#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) +#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) +#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) + + +#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) +#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) +#define START (LCD_CONTROL_BLOCK_BASE|0x08) +#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) +#define CMN (LCD_CONTROL_BLOCK_BASE|0x10) +#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) +#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) +#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) +#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) +#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) +#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) + +#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) +#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) +#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) +#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) +#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) +#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) +#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) +#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) +#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) +#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) +#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) +#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) +#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) +#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) +#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) +#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) +#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) +#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) +#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) +#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) +#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) +#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) +#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) +#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) + +#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0) + +#define Current (LCD_CONTROL_BLOCK_BASE|0xC0) +#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4) +#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8) + + +#define SSICTL (SPI_BLOCK_BASE|0x00) +#define SSITIME (SPI_BLOCK_BASE|0x04) +#define SSITX (SPI_BLOCK_BASE|0x08) +#define SSIRX (SPI_BLOCK_BASE|0x0C) +#define SSIINTC (SPI_BLOCK_BASE|0x10) +#define SSIINTS (SPI_BLOCK_BASE|0x14) +#define SSIDBG1 (SPI_BLOCK_BASE|0x18) +#define SSIDBG2 (SPI_BLOCK_BASE|0x1C) +#define SSIID (SPI_BLOCK_BASE|0x20) + + +#define I2CSETUP (I2C_BLOCK_BASE|0x00) +#define I2CCTRL (I2C_BLOCK_BASE|0x04) + + +#define TIMER0LOAD (PWM_BLOCK_BASE|0x00) +#define TIMER0VALUE (PWM_BLOCK_BASE|0x04) +#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08) +#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C) +#define TIMER0RIS (PWM_BLOCK_BASE|0x10) +#define TIMER0MIS (PWM_BLOCK_BASE|0x14) +#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18) +#define PWM0OFF (PWM_BLOCK_BASE|0x1C) +#define TIMER1LOAD (PWM_BLOCK_BASE|0x20) +#define TIMER1VALUE (PWM_BLOCK_BASE|0x24) +#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28) +#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C) +#define TIMER1RIS (PWM_BLOCK_BASE|0x30) +#define TIMER1MIS (PWM_BLOCK_BASE|0x34) +#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38) +#define PWM1OFF (PWM_BLOCK_BASE|0x3C) +#define TIMERITCR (PWM_BLOCK_BASE|0x60) +#define TIMERITOP (PWM_BLOCK_BASE|0x64) +#define PWMCR (PWM_BLOCK_BASE|0x68) +#define PWMID (PWM_BLOCK_BASE|0x6C) +#define PWMMON (PWM_BLOCK_BASE|0x70) + + +#define GPIODATA (GPIO_BLOCK_BASE|0x00) +#define GPIODIR (GPIO_BLOCK_BASE|0x04) +#define GPIOIS (GPIO_BLOCK_BASE|0x08) +#define GPIOIBE (GPIO_BLOCK_BASE|0x0C) +#define GPIOIEV (GPIO_BLOCK_BASE|0x10) +#define GPIOIE (GPIO_BLOCK_BASE|0x14) +#define GPIORIS (GPIO_BLOCK_BASE|0x18) +#define GPIOMIS (GPIO_BLOCK_BASE|0x1C) +#define GPIOIC (GPIO_BLOCK_BASE|0x20) +#define GPIOOMS (GPIO_BLOCK_BASE|0x24) +#define GPIOPC (GPIO_BLOCK_BASE|0x28) + +#define GPIOID (GPIO_BLOCK_BASE|0x30) + + +#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) +#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) +#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) +#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) +#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10) +#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) + +void panel_init(struct mddi_client_caps *client_caps) +{ +} + +#endif //mddi + +void panel_poweron(void) +{ +} + +void panel_backlight(int on) +{ +} diff --git a/platform/pre3/panel.h b/platform/pre3/panel.h new file mode 100644 index 0000000..0154686 --- /dev/null +++ b/platform/pre3/panel.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __PLATFORM_MSM7X30_PANEL_H +#define __PLATFORM_MSM7X30_PANEL_H + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define LDO08_CNTRL 0x011 +#define LDO12_CNTRL 0x015 +#define LDO15_CNTRL 0x089 +#define LDO16_CNTRL 0x08A +#define LDO20_CNTRL 0x11F /* PM8058 only */ +#define LDO_LOCAL_EN_BMSK 0x80 + +#define SPI_SCLK 45 +#define SPI_CS 46 +#define SPI_MOSI 47 +#define SPI_MISO 48 + + +#endif diff --git a/platform/pre3/platform.c b/platform/pre3/platform.c new file mode 100644 index 0000000..b44e2a3 --- /dev/null +++ b/platform/pre3/platform.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * + * Copyright (c) 2012 xndcn + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include + +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include "gpio_hw.h" + +void platform_init_interrupts(void); +void platform_init_timer(); + +#define MB (1024*1024) +#define ARRAY_SIZE(a) (sizeof(a)/(sizeof((a)[0]))) + +static struct msm_gpio mmc_gpio_table[] = { + {GPIO_CFG(64, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_16MA), "MMC_SD_CLK"}, + {GPIO_CFG(65, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_CMD"}, + + {GPIO_CFG(66, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA3"}, + {GPIO_CFG(67, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA2"}, + {GPIO_CFG(68, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA1"}, + {GPIO_CFG(69, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),"MMC_SD_DATA0"}, + + {GPIO_CFG(115, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA4"}, + {GPIO_CFG(114, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA5"}, + {GPIO_CFG(113, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA),"MMC_SD_DATA6"}, + {GPIO_CFG(112, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),"MMC_SD_DATA7"}, +}; + +static uint32_t ticks_per_sec = 0; +/* Initialize DGT timer */ +void platform_init_timer(void) +{ + uint32_t val = 0; + + /* Disable timer */ + writel(0, DGT_ENABLE); + + /* Check for the hardware revision */ + val = readl(HW_REVISION_NUMBER); + val = (val >> 28) & 0x0F; + if(val >= 1) + writel(1, DGT_CLK_CTL); + +#if _EMMC_BOOT + ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */ +#else + ticks_per_sec = 6144000; /* Uses LPXO/4 (24.576 MHz / 4) */ +#endif +} + +/* Returns timer ticks per sec */ +uint32_t platform_tick_rate(void) +{ + return ticks_per_sec; +} + +void platform_early_init(void) +{ + platform_gpios_enable(mmc_gpio_table, ARRAY_SIZE(mmc_gpio_table)); + platform_init_interrupts(); + platform_init_timer(); +} + +void platform_init(void) +{ + +} + +void platform_uninit(void) +{ + printf("platform_uninit\n"); + mask_interrupt(INT_USB_OTG_HS); + mask_interrupt(INT_DEBUG_TIMER_EXP); + platform_uninit_timer(); +} + +void display_init(void) +{ + struct fbcon_config *fb_cfg; + + mddi_pmdh_clock_init(); + fb_cfg = mddi_init(); + fbcon_setup(fb_cfg); + platform_init_display(); + gfxconsole_start_on_display(); +} diff --git a/platform/pre3/rules.mk b/platform/pre3/rules.mk new file mode 100644 index 0000000..64ad405 --- /dev/null +++ b/platform/pre3/rules.mk @@ -0,0 +1,28 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +DEBUG := 2 + +ARCH := arm +ARM_CPU := cortex-a8 +CPU := generic + +DEFINES += ARM_CPU_CORE_SCORPION PLATFORM_MSM7X30=1 + +INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/target/$(TARGET)/include + + +DEVS += fbcon +MODULES += dev/fbcon + +OBJS += \ + $(LOCAL_DIR)/interrupts.o \ + $(LOCAL_DIR)/acpuclock.o \ + $(LOCAL_DIR)/panel.o \ + $(LOCAL_DIR)/display.o \ + $(LOCAL_DIR)/gpio.o \ + $(LOCAL_DIR)/platform.o + +LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld + +include platform/msm_shared/rules.mk + diff --git a/project/pre3.mk b/project/pre3.mk new file mode 100644 index 0000000..d6916d6 --- /dev/null +++ b/project/pre3.mk @@ -0,0 +1,28 @@ +# top level project rules for the pre3 project +# +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := pre3 + +MODULES += app/moboot +MODULES += lib/gfx +MODULES += lib/font +MODULES += lib/gfxconsole +MODULES += lib/atags +MODULES += lib/fs +MODULES += lib/bio +MODULES += lib/tga +MODULES += lib/ramdisk +MODULES += lib/zlib +MODULES += lib/bootlinux +MODULES += lib/uimage + +#DEFINES += WITH_DEBUG_DCC=1 +#DEFINES += WITH_DEBUG_UART=1 +#DEFINES += WITH_DEBUG_FBCON=1 + +DEFINES += _EMMC_BOOT=1 +DEFINES += DISABLE_MMC_DEBUG_SPEW +DEFINES += HANDLE_LINUX_KERNEL_ARGS +DEFINES += WITH_LIB_FS_EXT2=1 +DEFINES += MOBOOT_VERSION="\"0.3.5-pre3\"" diff --git a/target/pre3/atags.c b/target/pre3/atags.c new file mode 100644 index 0000000..7cfd0f4 --- /dev/null +++ b/target/pre3/atags.c @@ -0,0 +1,82 @@ +/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include +#include + +#define EBI1_ADDR_128M 0x08000000 +#define SIZE_1M 0x00100000 + + +static int scratch_addr = -1; + +unsigned* target_atag_mem(unsigned* ptr) +{ + /* ATAG_MEM */ + *ptr++ = 4; + *ptr++ = 0x54410002; + *ptr++ = 0x0cd00000; + *ptr++ = 0x00200000; + + *ptr++ = 4; + *ptr++ = 0x54410002; + *ptr++ = 0x0ff00000; + *ptr++ = 0x20000000; + return ptr; +} + +void *target_get_scratch_address(void) +{ + struct smem_ram_ptable ram_ptable; + unsigned i = 0; + + if (smem_ram_ptable_init(&ram_ptable)) + { + for (i = 0; i < ram_ptable.len; i++) + { + if ((ram_ptable.parts[i].attr == READWRITE) + && (ram_ptable.parts[i].domain == APPS_DOMAIN) + && (ram_ptable.parts[i].start != 0x0)) + { + if (ram_ptable.parts[i].size >= FASTBOOT_BUF_SIZE) + { + scratch_addr = ram_ptable.parts[i].start; + break; + } + } + } + } + else + { + dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n"); + ASSERT(0); + } + + return (void *)((scratch_addr == -1) ? EBI1_ADDR_128M : scratch_addr); +} diff --git a/target/pre3/gpiokeys.c b/target/pre3/gpiokeys.c new file mode 100644 index 0000000..01f91dc --- /dev/null +++ b/target/pre3/gpiokeys.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2011, James Sullins + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include + +int gpiokeys_poll(unsigned keylist) { + + int keys_result = 0; + if (keylist & KEY_UP) { + if (!gpio_get(KEY_UP_GPIO)) { + keys_result += KEY_UP; + } + } + + if (keylist & KEY_DOWN) { + if (!gpio_get(KEY_DOWN_GPIO)) { + keys_result += KEY_DOWN; + } + } + + if (keylist & KEY_SELECT) { + if (gpio_get(KEY_SELECT_GPIO) == 0) { + keys_result += KEY_SELECT; + } + } + + printf("vol up: %d, vol down: %d, select: %d\n", !gpio_get(KEY_UP_GPIO), !gpio_get(KEY_DOWN_GPIO), !gpio_get(KEY_SELECT_GPIO)); + + + return keys_result; +} + + +void gpiokeys_wait_select() +{ + unsigned keys, is_pressed; + + while (gpiokeys_poll(KEY_ALL)) { + thread_sleep(20); + } + + is_pressed = gpiokeys_poll(KEY_ALL); + while (1) { + thread_sleep(20); + keys = gpiokeys_poll(KEY_ALL); + if (is_pressed && !keys) { + if (is_pressed & KEY_SELECT) { + return; + } + } + is_pressed = keys; + } +} diff --git a/target/pre3/include/target/display.h b/target/pre3/include/target/display.h new file mode 100644 index 0000000..69cd4ac --- /dev/null +++ b/target/pre3/include/target/display.h @@ -0,0 +1,47 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef _TARGET_MSM7630_SURF_DISPLAY_H +#define _TARGET_MSM7630_SURF_DISPLAY_H + +#define TARGET_XRES 480 +#define TARGET_YRES 800 + +#define LCDC_FB_WIDTH 480 +#define LCDC_FB_HEIGHT 800 + +#define LCDC_HSYNC_PULSE_WIDTH_DCLK 8 +#define LCDC_HSYNC_BACK_PORCH_DCLK 184 +#define LCDC_HSYNC_FRONT_PORCH_DCLK 4 +#define LCDC_HSYNC_SKEW_DCLK 0 + +#define LCDC_VSYNC_PULSE_WIDTH_LINES 1 +#define LCDC_VSYNC_BACK_PORCH_LINES 2 +#define LCDC_VSYNC_FRONT_PORCH_LINES 3 + +#endif diff --git a/target/pre3/include/target/gpiokeys.h b/target/pre3/include/target/gpiokeys.h new file mode 100644 index 0000000..035e4fa --- /dev/null +++ b/target/pre3/include/target/gpiokeys.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2011, James Sullins + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _GPIOKEYS_H +#define _GPIOKEYS_H + +#define KEY_UP 1 +#define KEY_LEFT KEY_UP +#define KEY_DOWN 2 +#define KEY_RIGHT KEY_DOWN +#define KEY_SELECT 4 +#define KEY_CENTER KEY_SELECT +#define KEY_ALL (KEY_UP|KEY_DOWN|KEY_SELECT) + +#define KEY_UP_GPIO 43 +#define KEY_DOWN_GPIO 37 +#define KEY_SELECT_GPIO 40 + +extern int gpiokeys_poll(unsigned keylist); +extern void gpiokeys_wait_select(); + +#endif diff --git a/target/pre3/include/target/restart.h b/target/pre3/include/target/restart.h new file mode 100644 index 0000000..55d45cf --- /dev/null +++ b/target/pre3/include/target/restart.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2011, James Sullins + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _PLATFORM_APQ_TOUCHPAD_RESTART_H +#define _PLATFORM_APQ_TOUCHPAD_RESTART_H + +/* Palm specific */ +#define RESTART_REASON_SHUTDOWN 0x6f656d00 +#define RESTART_REASON_RECOVER 0x6f656d11 +#define RESTART_REASON_PANIC 0x6f656d22 +#define RESTART_REASON_DFU 0x6f656d33 +#define RESTART_REASON_REBOOT 0x6f656d44 +#define RESTART_REASON_LATE_BOOT 0x6f656d55 +#define RESTART_REASON_UPDATE 0x6f656d66 +#define RESTART_REASON_UNKNOWN 0x77665501 + +/* misc */ +#define RESTART_REASON_BOOTLOADER 0x77665500 +#define RESTART_REASON_RECOVERY 0x77665502 + +#endif diff --git a/target/pre3/init.c b/target/pre3/init.c new file mode 100644 index 0000000..7ed2626 --- /dev/null +++ b/target/pre3/init.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2009, Google Inc. + * All rights reserved. + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * + * Copyright (c) 2012 xndcn + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include "smem.h" +#include +#include + +extern unsigned int mmc_boot_main(unsigned char slot, unsigned int base); +static unsigned mmc_sdc_base[] = { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE}; + +void target_early_init() +{ + //close irq gpt0, which is used by bootie + mask_interrupt(INT_GPT0_TIMER_EXP); +} + +void target_init() +{ + unsigned base_addr; + unsigned char slot; + struct smem_ram_ptable ram_ptable; + + display_init(); + printf("scratch: 0x%x\n", target_get_scratch_address()); + printf("display init done\n"); + slot = 2; + base_addr = mmc_sdc_base[slot-1]; + mmc_boot_main(slot, base_addr); + printf("done loading from mmc\n"); +} + +void reboot_device(unsigned reboot_reason) +{ + reboot(reboot_reason); +} diff --git a/target/pre3/rules.mk b/target/pre3/rules.mk new file mode 100644 index 0000000..5c7f6d6 --- /dev/null +++ b/target/pre3/rules.mk @@ -0,0 +1,39 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared -I$(LK_TOP_DIR)/platform/pre3 + +PLATFORM := pre3 + +MEMBASE := 0x04600000 # EBI +MEMSIZE := 0x00100000 # 1MB + +BASE_ADDR := 0x04600000 + +TAGS_ADDR := BASE_ADDR+0x00000100 +KERNEL_ADDR := BASE_ADDR+0x00008000 +RAMDISK_ADDR := BASE_ADDR+0x01000000 +SCRATCH_ADDR := 0x01000000 +SCRATCH_SIZE := 64 +FASTBOOT_BUF_SIZE := 0x07800000 + + + +DEFINES += \ + SDRAM_SIZE=$(MEMSIZE) \ + MEMBASE=$(MEMBASE) \ + BASE_ADDR=$(BASE_ADDR) \ + TAGS_ADDR=$(TAGS_ADDR) \ + KERNEL_ADDR=$(KERNEL_ADDR) \ + RAMDISK_ADDR=$(RAMDISK_ADDR) \ + SCRATCH_ADDR=$(SCRATCH_ADDR) \ + SCRATCH_SIZE=$(SCRATCH_SIZE) \ + FASTBOOT_BUF_SIZE=$(FASTBOOT_BUF_SIZE) \ + MACH_TYPE=2507 + +DEFINES += DISPLAY_TYPE_MDDI=1 TARGET_MSM7630_SURF MDP4=1 +DEFINES += LCD_WIDTH=480 LCD_HEIGHT=800 + +OBJS += \ + $(LOCAL_DIR)/gpiokeys.o \ + $(LOCAL_DIR)/atags.o \ + $(LOCAL_DIR)/init.o diff --git a/target/pre3/tools/makefile b/target/pre3/tools/makefile new file mode 100755 index 0000000..94f47ca --- /dev/null +++ b/target/pre3/tools/makefile @@ -0,0 +1,45 @@ +#Makefile to generate appsboot.mbn + +ifeq ($(BOOTLOADER_OUT),.) +APPSBOOTHEADER_DIR := $(BUILDDIR) +else +APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../../ +endif + +SRC_DIR := target/$(TARGET)/tools +COMPILER := gcc + +ifeq ($(EMMC_BOOT), 1) + APPSBOOTHDR_FILES := EMMCBOOT.MBN +else + ifeq ($(BUILD_NANDWRITE), 1) + APPSBOOTHDR_FILES := + else + APPSBOOTHDR_FILES := appsboot.mbn + endif +endif + +APPSBOOTHEADER: $(APPSBOOTHDR_FILES) + + +appsboot.mbn: appsboothd.mbn $(OUTBIN) + cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw + cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn + rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn + +appsboothd.mbn: mkheader $(OUTBIN) + $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn + +EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN) + cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw + cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN + cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn + rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn + +emmc_appsboothd.mbn: mkheader $(OUTBIN) + $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn + +mkheader: $(SRC_DIR)/mkheader.c + ${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(SRC_DIR)/mkheader + cp $(SRC_DIR)/mkheader $(APPSBOOTHEADER_DIR)/mkheader + diff --git a/target/pre3/tools/mkheader.c b/target/pre3/tools/mkheader.c new file mode 100755 index 0000000..fda8b67 --- /dev/null +++ b/target/pre3/tools/mkheader.c @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2007, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +int print_usage(){ + fprintf(stderr,"usage: mkheader \n"); + fprintf(stderr," mkheader \n"); + fprintf(stderr," mkheader \n"); + fprintf(stderr," mkheader \n\n"); + fprintf(stderr,"bin: Input raw appsbl binary\n"); + fprintf(stderr,"hdr: Output of appsbl header location\n"); + fprintf(stderr,"outbin: Output of the signed or unsigned apps boot location\n"); + fprintf(stderr,"maxsize: Maximum size for certificate chain\n"); + fprintf(stderr,"certchain: Output of the certchain location\n"); + fprintf(stderr,"files: Input format ...\n"); + fprintf(stderr,"certificate chain: Files will be concatenated in order to create the certificate chain\n\n"); + return -1; +} + +int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size){ + unsigned bytes_left = size; + char buf[buff_size]; + int ret = 0; + + while(bytes_left){ + fread(buf, sizeof(char), buff_size, in); + if(!feof(in)){ + bytes_left -= fwrite(buf, sizeof(char), buff_size, out); + }else + bytes_left = 0; + } + ret = ferror(in) | ferror(out); + if(ret) + fprintf(stderr, "ERROR: Occured during file concatenation\n"); + return ret; +} + +int main(int argc, char *argv[]) +{ + struct stat s; + unsigned size, base; + int unified_boot = 0; + unsigned unified_boot_magic[20]; + unsigned non_unified_boot_magic[10]; + unsigned magic_len = 0; + unsigned *magic; + unsigned cert_chain_size = 0; + unsigned signature_size = 0; + int secure_boot = 0; + int fd; + + if(argc < 3) { + return print_usage(); + } + + if (argc == 4) { + if(!strcmp("unified-boot",argv[3])) { + unified_boot = 1; + }else if(!strcmp("secure-boot",argv[3])){ + fprintf(stderr, + "ERROR: Missing arguments: [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n"); + return print_usage(); + } + else if(!strcmp("unsecure-boot",argv[3])){ + fprintf(stderr,"ERROR: Missing arguments: outbin directory\n"); + return print_usage(); + } + } + + if (argc > 4) { + if(!strcmp("secure-boot",argv[3])) { + if(argc < 9 && argc != 6){ + fprintf(stderr, + "ERROR: Missing argument(s): [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n"); + return print_usage(); + } + secure_boot = 1; + signature_size = 256; //Support SHA 256 + cert_chain_size = atoi(argv[5]); + } + } + + if(stat(argv[1], &s)) { + perror("cannot stat binary"); + return -1; + } + + if(unified_boot) { + magic = unified_boot_magic; + magic_len = sizeof(unified_boot_magic); + } else { + magic = non_unified_boot_magic; + magic_len = sizeof(non_unified_boot_magic); + } + + size = s.st_size; +#if MEMBASE + base = MEMBASE; +#else + base = 0; +#endif + + printf("Image Destination Pointer: 0x%x\n", base); + + magic[0] = 0x00000005; /* appsbl */ + magic[1] = 0x00000003; //Flash_partition_version /* nand */ + magic[2] = 0x00000000; //image source pointer + magic[3] = base; //image destination pointer + magic[4] = size + cert_chain_size + signature_size; //image size + magic[5] = size; //code size + magic[6] = base + size; + magic[7] = signature_size; + magic[8] = size + base + signature_size; + magic[9] = cert_chain_size; + + if (unified_boot == 1) + { + magic[10] = 0x33836685; /* cookie magic number */ + magic[11] = 0x00000001; /* cookie version */ + magic[12] = 0x00000002; /* file formats */ + magic[13] = 0x00000000; + magic[14] = 0x00000000; /* not setting size for boot.img */ + magic[15] = 0x00000000; + magic[16] = 0x00000000; + magic[17] = 0x00000000; + magic[18] = 0x00000000; + magic[19] = 0x00000000; + } + + fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644); + if(fd < 0) { + perror("cannot open header for writing"); + return -1; + } + if(write(fd, magic, magic_len) != magic_len) { + perror("cannot write header"); + close(fd); + unlink(argv[2]); + return -1; + } + close(fd); + + if (secure_boot && argc > 6){ + FILE * input_file; + FILE * output_file; + unsigned buff_size = 1; + char buf[buff_size]; + unsigned bytes_left; + unsigned current_cert_chain_size = 0; + int padding_size = 0; + int i; + + if((output_file = fopen(argv[6], "wb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + printf("Certificate Chain Output File: %s\n", argv[6]); + + for (i = 8; i < argc; i++){ + if((input_file = fopen(argv[i], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[i], &s); + bytes_left = s.st_size; + current_cert_chain_size += bytes_left; + if (cat(input_file, output_file, bytes_left, buff_size)) + return -1; + fclose(input_file); + } + + //Pad certifcate chain to the max expected size from input + memset(buf, 0xFF, sizeof(buf)); + padding_size = cert_chain_size - current_cert_chain_size; + + if(padding_size <0){ + fprintf(stderr, "ERROR: Input certificate chain (Size=%d) is larger than the maximum specified (Size=%d)\n", + current_cert_chain_size, cert_chain_size); + return -1; + } + + bytes_left = (padding_size > 0) ? padding_size : 0; + while(bytes_left){ + if(!ferror(output_file)) + bytes_left -= fwrite(buf, sizeof(buf), buff_size, output_file); + else{ + fprintf(stderr, "ERROR: Occured during certifcate chain padding\n"); + return -1; + } + } + fclose(output_file); + + //Concat and combine to signed image. Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN] + if((output_file = fopen(argv[4], "wb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + printf("Image Output File: %s\n", argv[4]); + + //Header + if((input_file = fopen(argv[2], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[2], &s); + if (cat(input_file, output_file, s.st_size, buff_size)) + return -1; + fclose(input_file); + + //Raw Appsbl + if((input_file = fopen(argv[1], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[1], &s); + if(cat(input_file, output_file, s.st_size, buff_size)) + return -1; + fclose(input_file); + + //Signature + if((input_file = fopen(argv[7], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[7], &s); + if(cat(input_file, output_file, s.st_size, buff_size)) + return -1; + fclose(input_file); + + //Certifcate Chain + if((input_file = fopen(argv[6], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + if(cat(input_file, output_file, (current_cert_chain_size + padding_size), buff_size)) + return -1; + fclose(input_file); + + fclose(output_file); + + }else if(argc == 5 || argc == 6){ + FILE * input_file; + FILE * output_file; + unsigned buff_size = 1; + char buf[buff_size]; + + //Concat and combine to unsigned image. Format [HDR][RAW APPSBOOT] + if((output_file = fopen(argv[4], "wb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + printf("Image Output File: %s\n", argv[4]); + + //Header + if((input_file = fopen(argv[2], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[2], &s); + if (cat(input_file, output_file, s.st_size, buff_size)) + return -1; + fclose(input_file); + + //Raw Appsbl + if((input_file = fopen(argv[1], "rb"))==NULL){ + perror("ERROR: Occured during fopen"); + return -1; + } + stat(argv[1], &s); + if(cat(input_file, output_file, s.st_size, buff_size)) + return -1; + fclose(input_file); + fclose(output_file); + } + + printf("Done execution\n"); + + return 0; +}