197 lines
7.3 KiB
C
197 lines
7.3 KiB
C
/*
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* Copyright (c) 2007, Google Inc.
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* All rights reserved.
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*
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* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Code Aurora nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <dev/gpio.h>
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#include <kernel/thread.h>
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#include "gpio_hw.h"
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#include "panel.h"
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#include <platform/machtype.h>
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#include <dev/lcdc.h>
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#if DISPLAY_TYPE_MDDI
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#include <mddi.h>
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#define MDDI_CLIENT_CORE_BASE 0x108000
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#define LCD_CONTROL_BLOCK_BASE 0x110000
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#define SPI_BLOCK_BASE 0x120000
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#define I2C_BLOCK_BASE 0x130000
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#define PWM_BLOCK_BASE 0x140000
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#define GPIO_BLOCK_BASE 0x150000
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#define SYSTEM_BLOCK1_BASE 0x160000
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#define SYSTEM_BLOCK2_BASE 0x170000
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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
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#define START (LCD_CONTROL_BLOCK_BASE|0x08)
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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
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#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
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#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
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#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
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#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
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#define SSICTL (SPI_BLOCK_BASE|0x00)
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#define SSITIME (SPI_BLOCK_BASE|0x04)
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#define SSITX (SPI_BLOCK_BASE|0x08)
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#define SSIRX (SPI_BLOCK_BASE|0x0C)
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#define SSIINTC (SPI_BLOCK_BASE|0x10)
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#define SSIINTS (SPI_BLOCK_BASE|0x14)
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#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
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#define SSIID (SPI_BLOCK_BASE|0x20)
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#define I2CSETUP (I2C_BLOCK_BASE|0x00)
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#define I2CCTRL (I2C_BLOCK_BASE|0x04)
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#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
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#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
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#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
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#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
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#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
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#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
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#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
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#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
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#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
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#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
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#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
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#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
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#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
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#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
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#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
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#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
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#define TIMERITCR (PWM_BLOCK_BASE|0x60)
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#define TIMERITOP (PWM_BLOCK_BASE|0x64)
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#define PWMCR (PWM_BLOCK_BASE|0x68)
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#define PWMID (PWM_BLOCK_BASE|0x6C)
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#define PWMMON (PWM_BLOCK_BASE|0x70)
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#define GPIODATA (GPIO_BLOCK_BASE|0x00)
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#define GPIODIR (GPIO_BLOCK_BASE|0x04)
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#define GPIOIS (GPIO_BLOCK_BASE|0x08)
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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
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#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
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#define GPIOIE (GPIO_BLOCK_BASE|0x14)
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#define GPIORIS (GPIO_BLOCK_BASE|0x18)
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#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
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#define GPIOIC (GPIO_BLOCK_BASE|0x20)
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#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
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#define GPIOPC (GPIO_BLOCK_BASE|0x28)
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#define GPIOID (GPIO_BLOCK_BASE|0x30)
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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
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#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
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void panel_init(struct mddi_client_caps *client_caps)
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{
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}
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#endif //mddi
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void panel_poweron(void)
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{
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}
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void panel_backlight(int on)
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{
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}
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